Hello Unregistered ,
Thanks for the explanation. I misinterpreted these paragraphs. My understanding was to have ASYNC cleared and use Fosc/4. Ioannis
The SYNC block uses FOSC/4 as its sync clock, so it's difficult to use it if it's using FOSC/4 as its input source for counting too. 9966 for 16-bit read/write see sec 20.1.1.1: 9965 In...
Sure it is. Inside the ISR, Timer 0 is stopped, reloaded and restarted. I think is it obligatory to use Fosc/4. Unless I misunderstood the DS. Then why is it necessary to use ASYNC=1? Could...
Two things... Since you're using FOSC/4 as the source, set ASYNC bit in T0CON1. Also, when using 16 bit mode (MD16=1) you should always write TMR0H then TMR0L in that order so that the high...
looks like not reloading the tmr count every ms....... after first int, tmr counter looping from 0 .....???
Tried the files and indeed it worked OK. Sort off... I tried to setup the Timer 0 as 16bit timer, cloked by Fosc/4 with system clock at 64MHz. Reload value $C187 The toggle happens every 4...
Thanks Richard. Ioannis
sheldon sent me these for a project i was assisting with. it all seemed to work
I wonder if anyone managed to work with DT-INTS18 with the K42 series chips. The latest DT_INTS-18_K42c.bas file that tumbleweed posted (on this closed thread...
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Re: K42 and Timer Interrupts
Thanks for the explanation.
Ioannis - 28th April 2025, 19:28I misinterpreted these paragraphs. My understanding was to have ASYNC cleared and use Fosc/4.
Ioannis