8MHz & Fosc/4 = 2MHz = 0.5Us per instruction cycle.
Id 1:256 prescaler, it will count 256 instruction cycle before incrementing TMR0.
With a TMR0 preset to 176 and a prescaler of 256 it will interrupt every 10ms.
Skimask, you say:
"Tmr0 overflows every 256 instruction cycles, 7812.5 timers per second".
I don't get it.
256*0.5ns = 128 ns per overflow if 1:1 prescaler.
1000000000ns / 128 = 7812500 iterations per second




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