Skimask, you say:
"Tmr0 overflows every 256 instruction cycles, 7812.5 timers per second".
I don't get it.
256*0.5ns = 128 ns per overflow if 1:1 prescaler.
1000000000ns / 128 = 7812500 iterations per second
At 8Mhz, there are 2,000,000 instructions cycles per second.
Assuming a 1:1 prescaler, with an 8 bit counter, you'll get 7812.5 Tmr0 overflow interrupts per second.
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