SOLVED: How can I reduce ADC jitter

[Demon]

SOLVED: Noisy VDD/VSS using DC-DC converter. ADC stopped bouncing after using a 7805.

https://picbasic.co.uk/forum/showthr...527#post156527

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16F18877

- Using fixed input on ADC pin (1K to VDD, 1K to VSS - simulating pot at 50%)
- The ADC will drift from 498 to 509.

HSEROUTs on Serial Communicator:

Low=00498 High=00509

Is there anything in the registers that I can "tune" for the ADC?

#CONFIG
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
    __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_OFF & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF
    __config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG

DEFINE OSC 32

DEFINE  ADC_BITS 10                 ' 10-bit Analog to digital

define  CCP1_REG     0              ' Must clear unused CCP pins or else unpredictable results
DEFINE  CCP1_BIT     0
define  CCP2_REG     0
DEFINE  CCP2_BIT     0
DEFINE  CCP3_REG     0
DEFINE  CCP3_BIT     0
define  CCP4_REG     0
DEFINE  CCP4_BIT     0
define  CCP5_REG     0              ' Must clear unused CCP pins or else unpredictable results
DEFINE  CCP5_BIT     0

DEFINE  HSER_RXREG PORTC
DEFINE  HSER_RXBIT 7
DEFINE  HSER_TXREG PORTC
DEFINE  HSER_TXBIT 6

DEFINE  HSER_RCSTA 90h              ' Enable serial port & continuous receive
DEFINE  HSER_TXSTA 24h              ' Enable transmit, BRGH = 1
Define  HSER_BAUD 115200
DEFINE  HSER_CLROERR 1              ' Clear overflow automatically
DEFINE  HSER_SPBRGH  0
DEFINE  HSER_SPBRG  68

BAUDCON.3 = 1                       ' Enable 16 bit baudrate generator

RA4PPS = 0                          ' Disable CCP5
RB0PPS = 0                          ' Disable CCP4
RB5PPS = 0                          ' Disable CCP3
RC1PPS = 0                          ' Disable CCP2
RC2PPS = 0                          ' Disable CCP1

IOCAP = %00000000                               'IOC Positive Edge, low-to-high
IOCAN = %00000000                               'IOC Negative Edge, from high-to-low
IOCBP = %00000000                               'IOC Positive Edge, low-to-high
IOCBN = %00000000                               'IOC Negative Edge, from high-to-low
IOCCP = %00000000                               'IOC Positive Edge, low-to-high
IOCCN = %00000000                               'IOC Negative Edge, from high-to-low
'IOCDP = %00000000                              '...not available
'IOCDN = %00000000                              '...not available
'IOCEP = %00000000                              '...not available
'IOCEN = %00000000                              '...not available

WPUA = %00000000                        ' Pull-up resistors
WPUB = %00000000
WPUC = %00000000
WPUD = %00000000
WPUE = %00000000

INLVLA = %00000000                      ' TTL input level
INLVLB = %00000000
INLVLC = %00000000
INLVLD = %00000000
'INLVLE = %00000000                      ' ...only available on E3 / MCLR pin

ADCON0 = %10000100                      ' ADC CONTROL REGISTER 0
ADCLK  = %00111111                      ' ADC CLOCK SELECTION REGISTER
'ADPCH  = %00011010                      ' Channel 26 - D2

ANSELA = %00000000
ANSELB = %00000000
ANSELC = %00000000
ANSELD = %00000110                      ' Pin D2 = ADC input, NavCom
                                        ' Pin D1 = ADC input, Glareshield
ANSELE = %00000000

TRISA = %00000000                       
TRISB = %00000000                       
TRISC = %00000000                       
TRISD = %00000110                       
TRISE = %00000000

include "I:\Project_v2\PBP\PBP_Includes\USART.bas"

ADCInput                var word

LowADC                  var word
HighADC                 var word

    Pause 1                                     ' Let PIC stabilize

    LowADC = 1023
    HighADC = 0
    AdcInput = 0

Mainloop:

    adcin 26, AdcInput
    
    if AdcInput < LowADC then LowADc = AdcInput
    if AdcInput > HighADC then HighADC = AdcInput
        
    hserout [   "Low=", dec5 LowADC, "  High=", DEC5 HighADC, 10  ]                             
 
    goto mainloop
end

I was getting desperate with the drift on the pots, so I thought I'd do a control run using resistors.

I expected it to remain the same or very close, but I'm still getting drift.

[richard]

50mV of noise on the power supply would do that.
using FVR as adc ref might help a little and or a better regulator for the pots

[Demon]

I use a DC-DC converter to lower 12V down to 5V for the entire circuit.

Would a dedicated 7805 for the pots be a "meaningful" improvement?

I'll have up to 10 pots in the final circuit. Right now I'm trying to get 1 ADC working well.

[richard]

Would a dedicated 7805 for the pots be a "meaningful" improvement?

the first step is to measure the noise on the power rail and then to determine if that's an issue, there is no point adding a regulator for the pots if the adc pos reference is noisy

[Ioannis]

Based on the fact that you are using Power Supply as a reference voltage for the ADC:

1. the Power Supply noise is random and in the length of time it would have very minimal effect on the adc average value.

2. you are feeding the ADC input from a resistor divider that is connected to the Vdd, where also the reference voltage is connected to. It is called ratiometric and should zero the effect of regulator voltage drift. If the voltage of the Resistor divider changes by x % then the reference voltage will change by x % too. So eventually no drift should happen.

What you experience is strange and should not happen.

Needs more investigation.

If you heat or cool the PIC chip, is there any change?

Ioannis

P.S. If you finally use external Voltage reference, that is reasonably stable, I feel that the results will be even worse, because then the Vdd change will have maximum effect on the voltage sample.

[Ioannis]

The Vdd that resistors are connected to, is the exact same point that PIC Vdd pin is connected also?

Ioannis

[Aussie Barry]

16F18877


Is there anything in the registers that I can "tune" for the ADC?

The PIC16F18877 has an Analog-to-Digital converter with Computation
These post-processing functions are applied to the ADC conversion result and include averaging and low-pass filtering.

Cheers
Barry

[richard]

What happens if the wiper voltage exceeds the FVR voltage?

Ain specs from datasheet




at best the top range of the pot would be useless

[Ioannis]

Using FVR will make things worse...

Ioannis

[Demon]

I thought I'd step back and check VDD and VSS using my SDS1104 scope.

This is at 50mV:




Is it realistic to expect no drift on ADC with this much noise on my lines?

[Demon]

CONFIRMED: Noisy power definitely messes up everything when the PIC tries to compare the "wiper" reading with VDD/VSS, even using two 1K resistors to simulate 50% pot.

I switched to a 7805 supply and put back my "supposedly dirty" potentiometer. ADC low/high was back to a steady reading no matter where I turned the pot.

I had code prepared using the techniques discussed in Melanie's ADC thread (or was it SORT, I don't remember). I got lost looking at the computational feature of the ADC in the 16F18877; that could have replaced my averaging routine and most likely reduced time.

At worse if I get a dirty pot, I can drop the 1-2 lower bits from the 10-bit reading and still get 512-256 resolution out of a maximum 1024.

[richard]

i have a 16f18875 , on a microchip HPC curiosity board, the adc is quite stable.
reading the onboard pot has a statistical result from over 3600 readings like this below. for 99.8% of reads its within 3 counts.
there is no adc problem to find.

0000,0000,0000,0000,0000,0000,0002,0001,0108,1754 1731 0003,0001,0000,0000,0000,0000,0000,0000,0000,0000


1731 reads are at the mean , 1754 are 1 count down 108 are 2 down 3 are 1 up ...etc

max variance is -4 to + 2 counts , the two extremes coincide with my air conditioner compressor cycling


until you figure what you are doing wrong to cause so much noise on your power rails you are just painting over the real problem

#CONFIG
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
    __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_ON & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_ON
    __config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG


    DEFINE OSC 32
    
    DEFINE DEBUG_REG PORTD
    DEFINE DEBUG_BIT 2      ;  if not used for pwr  
    DEFINE DEBUG_BAUD 9600
    DEFINE DEBUG_MODE 0 
    
    DEFINE ADC_BITS 10                 ' 10-bit Analog to digital
    DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS
    
    ANSELA = % 00000001                      ' Pin A0 = ADC
    TRISA = % 11101111                       ' Pin A4 = LED
    TRISD = % 11111011                       ' DEBUG 
    LATD.2 = 1                              ' DEBUG 
    clear
    LED VAR LATA.4
    i var byte
    j var word
    bucket                var WORD
    ADCinput             var WORD
    mean                  var WORD
    buckets               var word[21] 
    outlier                 var WORD                       
    LED = 1                                  'Proof of Life 
    PAUSE 2000  
    DEBUG 13,10,"READY",13,10 
    FVRCON = % 10000011
    ADCON0 = % 10010100
    ADREF  = % 00000000
    ADCLK  = 32
    LED=0


Mainloop:
    mean = 0
    for i = 0 to 9
    ADCIN 0, ADCinput
    mean = mean + ADCinput
    next
    mean = mean/10 
    DEBUG "mean ",DEC mean,13,10
    for j = 0 to 3599
    ADCIN 0, ADCinput
    
    bucket = mean-ADCinput
    i = bucket + 10
    
    if i>20 then  
      outlier =  outlier + 1
    else
      buckets[i]=buckets[i] + 1
    endif
    'DEBUG 13,10,"mean ",DEC mean," i ",dec i," read ",dec ADCinput,13,10
    
    PAUSE 5
    next
    DEBUG "readings " ,13,10
    DEBUG  dec4 buckets[0],",", dec4 buckets[1],","  , dec4 buckets[2],",", dec4 buckets[3],"," , dec4 buckets[4],","
    DEBUG  dec4 buckets[5],",", dec4 buckets[6],","  , dec4 buckets[7],",", dec4 buckets[8],"," , dec4 buckets[9],"  "
    DEBUG  dec4 buckets[10],"  "
    DEBUG  dec4 buckets[11],",", dec4 buckets[12],","  , dec4 buckets[13],",", dec4 buckets[14],"," , dec4 buckets[15],","
    DEBUG  dec4 buckets[16],",", dec4 buckets[17],","  , dec4 buckets[18],",", dec4 buckets[19],"," , dec4 buckets[20],13,10
    DEBUG  "outliers ",dec4 outlier 
    DEBUG  13,10
    for i = 0 to 20
      buckets[i] = 0
    next
    outlier = 0
      
    GOTO Mainloop
end

[Demon]

Yeah, i'll check if desktop power supplies are more stable, but I doubt it.

Then I'll gut my circuit; remove pwm and lcd logic and send adc to pc via usart.

If it doesn't work smooth with just a pot running, I've got other problems.


And that voltage divider test too.

[Demon]

1st test: Voltage divider 4K7-4K7 using TPS56637 5V 5A drop-down circuit.

ADC readings for voltage-divider:

9VDC wall adapter, 63-66
XP-581 set at 9VDC, 61-64
XP-605 set at 9VDC, 62-64

(Elenco desktop power supplies)

Naturally the pots jitter a bit more than the fixed divider.

Game plan:
1. remove the PWM and use a fix resistor for backlight.
2. feed the TPS56637 using a 9-12V battery.
3. try using 2 separate TPS56637 circuits:
- 1 for ADC (all inputs).
- 1 for PWM and LCD (all outputs).

The one for inputs "might' be replaced with an ordinary 7805 later. I don't need a lot of current to read pots, switches and encoders.

[Demon]

1. remove the PWM and use a fix resistor for backlight.

Used 270R resistor for backlight, disabled all PWM/HPWM functionality on code:

- ADC reading jumped to 430, no longer in the 60ies.
- ADC reading for pots also jumped up near 400, which is what I expected for pots near 50%.

(pot reading still went from 0 to 1024 before, so don't know what happened).

ADC reading on V/D still jumps from 428-430, turned power OFF and back ON, now it's 444-447, slowly creeping up as I type, now seeing 450 blink.

[richard]

1st test: Voltage divider 4K7-4K7 using TPS56637 5V 5A drop-down circuit.


ADC readings for voltage-divider:


9VDC wall adapter, 63-66
XP-581 set at 9VDC, 61-64
XP-605 set at 9VDC, 62-64

what any of that actually means needs way more explanation

more importantly what does the power rail look like noise wise ?

Used 270R resistor for backlight, disabled all PWM/HPWM functionality on code:

i assume that's now one resistor per each backlight

what is the volts across the backlight resistor ?

did you ever measure backlight current @ 5v ?