SOLVED: How can I reduce ADC jitter

[Demon]

what any of that actually means needs way more explanation...

It's just the ADC readings I display on the LCD to check for jitter.

more importantly what does the power rail look like noise wise ?...

I'm reconnecting the scope to see if it changed now that there's no PWM.

...i assume that's now one resistor per each backlight...

I use only 1 LCD for this

...what is the volts across the backlight resistor ?...

1.83V, but I think you wanted voltage divider voltages, no?

...did you ever measure backlight current @ 5v ?

with 270R = 6.7mA
direct 5V = 32mA

[richard]

i was just curious about the backlight's current for potential noise generation, it seemed the most likely candidate to generate that much noise via pwm control. but even at max I of 32mA it should not cause that much noise, so that's my idea's blown out of the water.

[Demon]

This is my gutted code, only 1 pot and 1 voltage divider, with LCD (no PWM):

I'm trying to use FVR, no idea if I got all settings for that feature.

Voltage at rail directly over V-D = 4.62V
Voltage on 4K7 ADC to VDD = 2.30V
Voltage on 4K7 ADC to VSS = 2.30V

But I noticed the voltages fluctuate by 0.02V easily while taking readings.

#CONFIG
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
    __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_OFF & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF
    __config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG

DEFINE OSC 32

DEFINE  ADC_BITS 10                 ' 10-bit Analog to digital
                                        
DEFINE  LCD_DREG      PORTB         ' Set LCD data port
DEFINE  LCD_DBIT      0             ' Set starting data bit
DEFINE  LCD_RSREG     PORTC         ' Set LCD register select port
DEFINE  LCD_RSBIT     4             ' Set LCD register select bit
DEFINE  LCD_EREG      PORTC         ' Set LCD enable port
DEFINE  LCD_EBIT      5             ' Set LCD enable bit
DEFINE  LCD_BITS      4             ' Set LCD bus size
DEFINE  LCD_LINES     4             ' Set number of lines on LCD
DEFINE  LCD_COMMANDUS 1000          ' Set command delay time in microseconds
DEFINE  LCD_DATAUS    50            ' Set data delay time in microseconds

FVRCON = %10000011                  ' FIXED VOLTAGE REFERENCE CONTROL REGISTER
'   bit 7   FVREN: Fixed Voltage Reference Enable bit
'       --->    1 = Fixed Voltage Reference is enabled
'               0 = Fixed Voltage Reference is disabled
'   bit 6   FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
'               1 = Fixed Voltage Reference output is ready for use
'               0 = Fixed Voltage Reference output is not ready or not enabled
'   bit 5   TSEN: Temperature Indicator Enable bit(3)
'               1 = Temperature Indicator is enabled
'               0 = Temperature Indicator is disabled
'   bit 4   TSRNG: Temperature Indicator Range Selection bit(3)
'               1 = VOUT = VDD - 4VT (High Range)
'               0 = VOUT = VDD - 2VT (Low Range)
'   bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
'               11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2)
'               10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2)
'               01 = Comparator FVR Buffer Gain is 1x, (1.024V)
'               00 = Comparator FVR Buffer is off
'   bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
'       --->    11 = ADC FVR Buffer Gain is 4x, (4.096V)(2)
'               10 = ADC FVR Buffer Gain is 2x, (2.048V)(2)
'               01 = ADC FVR Buffer Gain is 1x, (1.024V)
'               00 = ADC FVR Buffer is off
'
' Note  1: FVRRDY is always ‘1’ for PIC16F18855/75 devices only.
'       2: Fixed Voltage Reference output cannot exceed VDD.

ADCON0 = %10000100                  ' ADC CONTROL REGISTER 0
'   bit 7   ADON: ADC Enable bit
'        --->   1 = ADC is enabled
'               0 = ADC is disabled
'   bit 6   ADCONT: ADC Continuous Operation Enable bit
'               1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is
'                   set) or until ADGO is cleared (regardless of the value of ADSOI)
'        --->   0 = ADGO is cleared upon completion of each conversion trigger
'   bit 5   Unimplemented: Read as ‘0’
'   bit 4   ADCS: ADC Clock Selection bit
'               1 = Clock supplied from FRC dedicated oscillator
'        --->   0 = Clock supplied by FOSC, divided according to ADCLK register
'   bit 3   Unimplemented: Read as ‘0’
'   bit 2   ADFRM0: ADC results Format/alignment Selection
'        --->   1 = ADRES and ADPREV data are right-justified
'               0 = ADRES and ADPREV data are left-justified, zero-filled
'   bit 1   Unimplemented: Read as ‘0’
'   bit 0   ADGO: ADC Conversion Status bit
'               1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is
'                   cleared by hardware as determined by the ADCONT bit
'        --->   0 = ADC conversion completed/not in progress

ADCLK = %00111111                   ' ADC CLOCK SELECTION REGISTER
'   bit 7-6 Unimplemented: Read as ‘0’
'   bit 5-0 ADCCS<5:0>: ADC Conversion Clock Select bits
'        --->   111111 = FOSC/128
'               111110 = FOSC/126
'               111101 = FOSC/124
'                  •
'               000000 = FOSC/2

ANSELA = %00001001                      ' Pin A3 = ADC (voltage divider)
                                        ' Pin A0 = ADC (B5K)
ANSELB = %00000000
ANSELC = %00000000

TRISA = %00001001                       ' Pin A3 = ADC input 3
                                        ' Pin A0 = ADC input 0
TRISB = %00000000
TRISC = %00000000

ADCinput            var WORD

OldADC0             var WORD
OldADC3             var WORD
NewADC0             var WORD
NewADC3             var WORD

    Pause 100                           ' Let PIC and LCD stabilize
    ADCinput = 0
    OldADC0 = 9999      : OldADC3 = 9999
    NewADC0 = 0         : NewADC3 = 0

    LCDOUT $FE, 1 : Pauseus 1
    LCDOUT $FE, $80, "      ADC test" : Pauseus 1
    LCDOUT $FE, $94, "ADC0:       B5K" : Pauseus 1
    LCDOUT $FE, $D4, "ADC3:       Volt-Div" : Pauseus 1

Mainloop:

rem                             ADC 0

    adcin 0, ADCinput
    NewADC0 = 1023 - ADCinput           ' inverted so pot goes from 0 to 1024
    
    if NewADC0 <> oldadc0 then
        oldadc0 = NewADC0
        LCDOUT $FE, $94+6, DEC4 oldadc0 : Pauseus 1
    endif


rem                             ADC 3

    adcin 3, ADCinput
    NewADC3 = ADCinput

    if NewADC3 <> oldadc3 then
        oldadc3 = NewADC3
        LCDOUT $FE, $D4+6, DEC4 oldadc3 : Pauseus 1
    endif

  GOTO Mainloop
end

I'm setting up my scope to read both rails used by the pot and voltage divider.

[Demon]

This is what it looks like.




(I don't talk loud cause wife is sleeping)

[richard]

the first thing i notice is you have not set a sample time , not sure if or what the defa may be

try this
DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS


secondly the adcin command has often been accused of wonky readings when the channel is changed

try this known work around of dual reads after a ch change

 Mainloop:

rem                             ADC 0
    adcin 0, ADCinput
    adcin 0, ADCinput
    NewADC0 = 1023 - ADCinput           ' inverted so pot goes from 0 to 1024
    
    if NewADC0 <> oldadc0 then
        oldadc0 = NewADC0
        LCDOUT $FE, $94+6, DEC4 oldadc0 : Pauseus 1
    endif




rem                             ADC 3
    adcin 3, ADCinput
    adcin 3, ADCinput
    NewADC3 = ADCinput


    if NewADC3 <> oldadc3 then
        oldadc3 = NewADC3
        LCDOUT $FE, $D4+6, DEC4 oldadc3 : Pauseus 1
    endif


  GOTO Mainloop
end

[richard]

if your scope probes are ac coupled to measure rail noise [ as they should be ] then the DC offsets visible on the scope are not coming from your circuit the scope provides them , the drift you see is random, for stability each and every scope probe gnd reference lead needs to be connected to the same point


ps warning , do not try to measure rails that don't share a common gnd reference , or exceed the scopes safe working voltage

[richard]

raw adc readings of x + or - 1 count is as good as it ever gets
+-2 is very good +-3 is typical result for a designed system
what are your expectations ?

[Demon]

raw adc readings of x + or - 1 count is as good as it ever gets
+-2 is very good +-3 is typical result for a designed system
what are your expectations ?

Coupling changed to AC.


1. Honestly I expected no jitter on the voltage-divider, thinking FVR would remove 1/2 the instability, leaving only VS as a variable source for comparison.

2. As for the pots, I had no idea what "realistic" is, they don't mention that in google tutorials.

3. I'm sure I could get something useful out of 10-bit results. Just not sure how to go about massaging the result.

4. I also would have liked to try the ADC2 feature like AVERAGE. I assume it'a a hardware equivalent of what Melanie was doing.

[Demon]

if your scope probes are ac coupled to measure rail noise [ as they should be ] then the DC offsets visible on the scope are not coming from your circuit the scope provides them , the drift you see is random, for stability each and every scope probe gnd reference lead needs to be connected to the same point


ps warning , do not try to measure rails that don't share a common gnd reference , or exceed the scopes safe working voltage

Ok.


All rails come from the same source; 5VDC.

And they all share the ground to that circuit.

[Demon]

Added DEFINE and doubled the ADCIN, no change really.

But I did notice a vulnerability in my system. Watch this when I gently touch power leads to the rails.

[richard]

the problem you see does not exist , its the scopes reaction to having an large antenna [YOUR HAND] capacitively coupled to all of its inputs providing an overwhelming signal on it most sensitive ac input range, the scope is unable to provide the dc bias needed to keep the traces aligned in the overwhelmed state

[Demon]

the problem you see does not exist , its the scopes reaction to having an large antenna [YOUR HAND] capacitively coupled to all of its inputs providing an overwhelming signal on it most sensitive ac input range, the scope is unable to provide the dc bias needed to keep the traces aligned in the overwhelmed state

Excellent, so this won't be an issue since the drop-down circuit will be linked directly the the main board by headers.

[richard]

making any measurements on a dc signal other than the ac noise level using a scope that is ac coupled to the dc signal is meaningless

[Ioannis]

All your setup is on a Breadboard?

I can suspect that even low current PWM loads on a breadboard may cause such issues. The stray capacitance of these things is too mauch to have a reliable operation.

My test of ADC on a Picdem boards show rock-solid readings. But is of good design with a lot of grounds that you are missing on breadboards.

Ioannis