SOLVED: How can I reduce ADC jitter

[richard]

the first thing i notice is you have not set a sample time , not sure if or what the defa may be

try this
DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS


secondly the adcin command has often been accused of wonky readings when the channel is changed

try this known work around of dual reads after a ch change

 Mainloop:

rem                             ADC 0
    adcin 0, ADCinput
    adcin 0, ADCinput
    NewADC0 = 1023 - ADCinput           ' inverted so pot goes from 0 to 1024
    
    if NewADC0 <> oldadc0 then
        oldadc0 = NewADC0
        LCDOUT $FE, $94+6, DEC4 oldadc0 : Pauseus 1
    endif




rem                             ADC 3
    adcin 3, ADCinput
    adcin 3, ADCinput
    NewADC3 = ADCinput


    if NewADC3 <> oldadc3 then
        oldadc3 = NewADC3
        LCDOUT $FE, $D4+6, DEC4 oldadc3 : Pauseus 1
    endif


  GOTO Mainloop
end

[richard]

if your scope probes are ac coupled to measure rail noise [ as they should be ] then the DC offsets visible on the scope are not coming from your circuit the scope provides them , the drift you see is random, for stability each and every scope probe gnd reference lead needs to be connected to the same point


ps warning , do not try to measure rails that don't share a common gnd reference , or exceed the scopes safe working voltage

[richard]

raw adc readings of x + or - 1 count is as good as it ever gets
+-2 is very good +-3 is typical result for a designed system
what are your expectations ?

[Demon]

raw adc readings of x + or - 1 count is as good as it ever gets
+-2 is very good +-3 is typical result for a designed system
what are your expectations ?

Coupling changed to AC.


1. Honestly I expected no jitter on the voltage-divider, thinking FVR would remove 1/2 the instability, leaving only VS as a variable source for comparison.

2. As for the pots, I had no idea what "realistic" is, they don't mention that in google tutorials.

3. I'm sure I could get something useful out of 10-bit results. Just not sure how to go about massaging the result.

4. I also would have liked to try the ADC2 feature like AVERAGE. I assume it'a a hardware equivalent of what Melanie was doing.

[Demon]

ADCshift = NewADC0 >> 2

I shifted the results 2 bits, expecting to lose any jitter from 0 - 3, but I still get jitter.

I bet it's when a number jumps an upper bit, like 00100011 to 01000100.

I'm using 10-bit ADC, so chopping 2 bits already bring me down to 256 increments.

Bringing it down more won't solve when it's a higher jump, like 00111111 to 01000000


EDIT: Divide by 4 doesn't help either, I still get jitter, even on the voltage-divider.

[richard]

changing my test to rs 2 digits

jitter negligible

mean 159
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3596  0004,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 159
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3600  0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 159
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3598  0002,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 159

#CONFIG    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
    __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_ON & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_ON
    __config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG


    DEFINE OSC 32
    
    DEFINE DEBUG_REG PORTD
    DEFINE DEBUG_BIT 2      ;  if not used for pwr  
    DEFINE DEBUG_BAUD 9600
    DEFINE DEBUG_MODE 0 
    
    DEFINE ADC_BITS 10                 ' 10-bit Analog to digital
    DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS
    
    ANSELA = % 00000001                      ' Pin A0 = ADC
    TRISA = % 11101111                       ' Pin A4 = LED
    TRISD = % 11111011                       ' DEBUG 
    LATD.2 = 1                              ' DEBUG 
    clear
    LED VAR LATA.4
    i var byte
    j var word
    bucket              var WORD
    ADCinput            var WORD
    mean                var WORD
    buckets             var word[21] 
    outlier             var WORD                       
    LED = 1                                  'Proof of Life 
    PAUSE 2000  
    DEBUG 13,10,"READY",13,10 
    FVRCON = % 10000011
    ADCON0 = % 10010100
    ADREF  = % 00000000
    ADPRE  = 48
    ADCLK  = 32
    ADCAP  = 31
    LED=0


Mainloop:
    mean = 0
    for i = 0 to 9
    ADCIN 0, ADCinput
    mean = mean + ADCinput
    next
    mean = mean/40 ;average divide 4
    DEBUG "mean ",DEC mean,13,10
    for j = 0 to 3599
    ADCIN 0, ADCinput
    ADCinput=ADCinput>>2
    bucket = mean-ADCinput
    i = bucket + 10
    
    if i>20 then  
      outlier =  outlier + 1
    else
      buckets[i]=buckets[i] + 1
    endif
    'DEBUG 13,10,"mean ",DEC mean," i ",dec i," read ",dec ADCinput,13,10
    
    PAUSE 5
    next
    DEBUG "readings " ,13,10
    DEBUG  dec4 buckets[0],",", dec4 buckets[1],","  , dec4 buckets[2],",", dec4 buckets[3],"," , dec4 buckets[4],","
    DEBUG  dec4 buckets[5],",", dec4 buckets[6],","  , dec4 buckets[7],",", dec4 buckets[8],"," , dec4 buckets[9],"  "
    DEBUG  dec4 buckets[10],"  "
    DEBUG  dec4 buckets[11],",", dec4 buckets[12],","  , dec4 buckets[13],",", dec4 buckets[14],"," , dec4 buckets[15],","
    DEBUG  dec4 buckets[16],",", dec4 buckets[17],","  , dec4 buckets[18],",", dec4 buckets[19],"," , dec4 buckets[20],13,10
    DEBUG  "outliers ",dec4 outlier 
    DEBUG  13,10
    for i = 0 to 20
      buckets[i] = 0
    next
    outlier = 0
      
    GOTO Mainloop
end

[richard]

using the fvr gets slightly better result [mine is a 3.3v system]

mean 255
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3600  0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 255
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3600  0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 255
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3600  0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 255
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3600  0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 255
readings 
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000  3600  0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
outliers 0000
mean 255

#CONFIG    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_ON & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
    __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_ON & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_ON
    __config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG


    DEFINE OSC 32
    
    DEFINE DEBUG_REG PORTD
    DEFINE DEBUG_BIT 2      ;  if not used for pwr  
    DEFINE DEBUG_BAUD 9600
    DEFINE DEBUG_MODE 0 
    
    DEFINE ADC_BITS 10                 ' 10-bit Analog to digital
    DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS
    
    ANSELA = % 00000001                      ' Pin A0 = ADC
    TRISA = % 11101111                       ' Pin A4 = LED
    TRISD = % 11111011                       ' DEBUG 
    LATD.2 = 1                              ' DEBUG 
    clear
    LED VAR LATA.4
    i var byte
    j var word
    bucket              var WORD
    ADCinput            var WORD
    mean                var WORD
    buckets             var word[21] 
    outlier             var WORD                       
    LED = 1                                  'Proof of Life 
    PAUSE 2000  
    DEBUG 13,10,"READY",13,10 
    FVRCON = % 10000010;2.048v
    ADCON0 = % 10000100
    ADREF  = % 00000011,fvr
    ADCLK  = 16; faster clk
    LED=0


Mainloop:
    mean = 0
    for i = 0 to 9
    ADCIN 0, ADCinput
    mean = mean + ADCinput
    next
    mean = mean/40 
    DEBUG "mean ",DEC mean,13,10
    for j = 0 to 3599
    ADCIN 0, ADCinput
    ADCinput=ADCinput>>2
    bucket = mean-ADCinput
    i = bucket + 10
    
    if i>20 then  
      outlier =  outlier + 1
    else
      buckets[i]=buckets[i] + 1
    endif
    'DEBUG 13,10,"mean ",DEC mean," i ",dec i," read ",dec ADCinput,13,10
    
    PAUSE 5
    next
    DEBUG "readings " ,13,10
    DEBUG  dec4 buckets[0],",", dec4 buckets[1],","  , dec4 buckets[2],",", dec4 buckets[3],"," , dec4 buckets[4],","
    DEBUG  dec4 buckets[5],",", dec4 buckets[6],","  , dec4 buckets[7],",", dec4 buckets[8],"," , dec4 buckets[9],"  "
    DEBUG  dec4 buckets[10],"  "
    DEBUG  dec4 buckets[11],",", dec4 buckets[12],","  , dec4 buckets[13],",", dec4 buckets[14],"," , dec4 buckets[15],","
    DEBUG  dec4 buckets[16],",", dec4 buckets[17],","  , dec4 buckets[18],",", dec4 buckets[19],"," , dec4 buckets[20],13,10
    DEBUG  "outliers ",dec4 outlier 
    DEBUG  13,10
    for i = 0 to 20
      buckets[i] = 0
    next
    outlier = 0
      
    GOTO Mainloop
end

[richard]

Coupling changed to AC.

to measure ac noise on rail , noise hopefully in mV and not to many of them

Coupling changed to DC.

for any dc , logic measurements

1. Honestly I expected no jitter on the voltage-divider, thinking FVR would remove 1/2 the instability, leaving only VS as a variable source for comparison.

raw adc will never have no jitter

2. As for the pots, I had no idea what "realistic" is, they don't mention that in google tutorials.

the word you want here is resolution, if you had a 1k pot and 10 bit adc you could resolve it to 1 ohm steps in theory
but adc is always has +- count , jitter free might get to 255 steps, you need to design for the outcome desired

3. I'm sure I could get something useful out of 10-bit results. Just not sure how to go about massaging the result.

depending on noise and needed resolution there are ways , from simple division, averaging or oversampling

4. I also would have liked to try the ADC2 feature like AVERAGE. I assume it'a a hardware equivalent of what Melanie was doing.

its not designed to average more than one ch and need exclusive use of the adc but have a go

[Demon]

...its not designed to average more than one ch and need exclusive use of the adc but have a go

23.0 ANALOG-TO-DIGITAL CONVERTER WITH COMPUTATION (ADC2) MODULE

The Analog-to-Digital Converter with Computation (ADC2) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit.

We can't switch ADPCH manually between each Average?


About that bug to ADCIN twice:

23.1 ADC Configuration

Note: It is recommended that when switching from an ADC channel of a higher voltage to a channel of a lower voltage, the software selects the VSS channel before switching to the channel of the lower voltage.

I'm trying to switch ADPCH to 111100 = AVSS (Analog Ground) before each ADCIN to see if that fixes the problem.

They seem to mean when you change power rail, but maybe there's a bug when "the higher voltage" is within the same rail (like changing from 1V up to 4V).

I haven't studied your code yet, this is where I am at trying to get FVR and Average:

#CONFIG
__config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_ON
__config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
__config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_OFF & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
__config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF
__config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG

DEFINE OSC 32

DEFINE ADC_BITS 10 ' 10-bit Analog to digital
DEFINE ADC_SAMPLEUS 50 ' Set sampling time in uS

DEFINE LCD_DREG PORTB ' Set LCD data port
DEFINE LCD_DBIT 0 ' Set starting data bit
DEFINE LCD_RSREG PORTC ' Set LCD register select port
DEFINE LCD_RSBIT 4 ' Set LCD register select bit
DEFINE LCD_EREG PORTC ' Set LCD enable port
DEFINE LCD_EBIT 5 ' Set LCD enable bit
DEFINE LCD_BITS 4 ' Set LCD bus size
DEFINE LCD_LINES 4 ' Set number of lines on LCD
DEFINE LCD_COMMANDUS 1000 ' Set command delay time in microseconds
DEFINE LCD_DATAUS 50 ' Set data delay time in microseconds

FVRCON = %10000011 ' FIXED VOLTAGE REFERENCE CONTROL REGISTER
' bit 7 FVREN: Fixed Voltage Reference Enable bit
' ---> 1 = Fixed Voltage Reference is enabled
' 0 = Fixed Voltage Reference is disabled
' bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
' 1 = Fixed Voltage Reference output is ready for use
' 0 = Fixed Voltage Reference output is not ready or not enabled
' bit 5 TSEN: Temperature Indicator Enable bit(3)
' 1 = Temperature Indicator is enabled
' 0 = Temperature Indicator is disabled
' bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
' 1 = VOUT = VDD - 4VT (High Range)
' 0 = VOUT = VDD - 2VT (Low Range)
' bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
' 11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2)
' 10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2)
' 01 = Comparator FVR Buffer Gain is 1x, (1.024V)
' 00 = Comparator FVR Buffer is off
' bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
' ---> 11 = ADC FVR Buffer Gain is 4x, (4.096V)(2)
' 10 = ADC FVR Buffer Gain is 2x, (2.048V)(2)
' 01 = ADC FVR Buffer Gain is 1x, (1.024V)
' 00 = ADC FVR Buffer is off
'
' Note 1: FVRRDY is always ‘1’ for PIC16F18855/75 devices only.
' 2: Fixed Voltage Reference output cannot exceed VDD.

ADCON0 = %10000100 ' ADC CONTROL REGISTER 0
' bit 7 ADON: ADC Enable bit
' ---> 1 = ADC is enabled
' 0 = ADC is disabled
' bit 6 ADCONT: ADC Continuous Operation Enable bit
' 1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is
' set) or until ADGO is cleared (regardless of the value of ADSOI)
' ---> 0 = ADGO is cleared upon completion of each conversion trigger
' bit 5 Unimplemented: Read as ‘0’
' bit 4 ADCS: ADC Clock Selection bit
' 1 = Clock supplied from FRC dedicated oscillator
' ---> 0 = Clock supplied by FOSC, divided according to ADCLK register
' bit 3 Unimplemented: Read as ‘0’
' bit 2 ADFRM0: ADC results Format/alignment Selection
' ---> 1 = ADRES and ADPREV data are right-justified
' 0 = ADRES and ADPREV data are left-justified, zero-filled
' bit 1 Unimplemented: Read as ‘0’
' bit 0 ADGO: ADC Conversion Status bit
' 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is
' cleared by hardware as determined by the ADCONT bit
' ---> 0 = ADC conversion completed/not in progress

ADCON2 = %00101010 ' ADC CONTROL REGISTER 2
' bit 7 ADPSIS: ADC Previous Sample Input Select bits
' 1 = ADFLTR is transferred to ADPREV at start-of-conversion
' 0 = ADRES is transferred to ADPREV at start-of-conversion
' bit 6-4 ADCRS<2:0>: ADC Accumulated Calculation Right Shift Select bits
' 111 = Reserved
' 110 = Reserved
' 101 through 000:
' If ADMD = 100:
' Low-pass filter time constant is 2ADCRS, filter gain is 1:1
' If ADMD = 001, 010 or 011:
' ---> The accumulated value is right-shifted by ADCRS (divided by 2ADCRS)(2)
' Otherwise:
' Bits are ignored
' bit 3 ADACLR: ADC Accumulator Clear Command bit
' 1 = Initial clear of ADACC, ADAOV, and the sample counter. Bit is cleared by hardware.
' 0 = Clearing action is complete (or not started)
' bit 2-0 ADMD<2:0>: ADC Operating Mode Selection bits(1)
' 111 = Reserved
' 101 = Reserved
' 100 = Low-pass Filter mode
' 011 = Burst Average mode
' ---> 010 = Average mode
' 001 = Accumulate mode
' 000 = Basic (Legacy) mode
' Note 1: See Table 23-3 for Full mode descriptions.
' 2: All results of divisions using the ADCRS bits are truncated, not rounded.

ADCNT = %00001000 ' ADC CONVERSION COUNTER REGISTER
' bit 7-0 ADRPT<7:0>: ADC Conversion Counter
' Counts the number of times that the ADC is triggered. Determines when the threshold is checked for
' the Low-Pass Filter, Burst Average, and Average Computation modes. Count saturates at 0xFF and
' does not roll-over to 0x00.

ADCLK = %00111111 ' ADC CLOCK SELECTION REGISTER
' bit 7-6 Unimplemented: Read as ‘0’
' bit 5-0 ADCCS<5:0>: ADC Conversion Clock Select bits
' ---> 111111 = FOSC/128
' 111110 = FOSC/126
' 111101 = FOSC/124
' •
' 000000 = FOSC/2

ADREF = %00000011 ' ADC REFERENCE SELECTION REGISTER
' bit 7-5 Unimplemented: Read as ‘0’
' bit 4 ADNREF: ADC Negative Voltage Reference Selection bit
' 1 = VREF- is connected to VREF- pin
' ---> 0 = VREF- is connected to AVSS
' bit 3-2 Unimplemented: Read as ‘0’
' bit 1-0 ADPREF: ADC Positive Voltage Reference Selection bits
' ---> 11 = VREF+ is connected to FVR_buffer 1
' 10 = VREF+ is connected to VREF+ pin
' 01 = Reserved
' 00 = VREF+ is connected to VDD

ADPCH = %00000000 ' ADC POSITIVE CHANNEL SELECTION REGISTER
' bit 7-6 Unimplemented: Read as ‘0’
' bit 5-0 ADPCH<5:0>: ADC Positive Input Channel Selection bits
' 111111 = Fixed Voltage Reference (FVR)
' 111110 = DAC1 output
' 111101 = Temperature Indicator
' ---> 111100 = AVSS (Analog Ground)
' 111011 = Reserved. No channel connected.
' •
' •
' •
' 100010 = ANE2 * 16F18877 only
' 100001 = ANE1 * 16F18877 only
' 100000 = ANE0 * 16F18877 only
' 011111 = AND7 * 16F18877 only
' 011110 = AND6 * 16F18877 only
' 011101 = AND5 * 16F18877 only
' 011100 = AND4 * 16F18877 only
' 011011 = AND3 * 16F18877 only
' 011010 = AND2 * 16F18877 only
' 011001 = AND1 * 16F18877 only
' 011000 = AND0 * 16F18877 only
' 010111 = ANC7
' 010110 = ANC6
' 010101 = ANC5
' 010100 = ANC4
' 010011 = ANC3
' 010010 = ANC2
' 010001 = ANC1
' 010000 = ANC0
' 001111 = ANB7
' 001110 = ANB6
' 001101 = ANB5
' 001100 = ANB4
' 001011 = ANB3
' 001010 = ANB2
' 001001 = ANB1
' 001000 = ANB0
' 000111 = ANA7
' 000110 = ANA6
' 000101 = ANA5
' 000100 = ANA4
' 000011 = ANA3
' 000010 = ANA2
' 000001 = ANA1
' 000000 = ANA0

ANSELA = %00001001 ' Pin A3 = ADC (voltage divider)
' Pin A0 = ADC (B5K)
ANSELB = %00000000
ANSELC = %00000000

TRISA = %00001001 ' Pin A3 = ADC input 3
' Pin A0 = ADC input 0
TRISB = %00000000
TRISC = %00000000

AVSS var byte
AVSS = %00111100 ' AVSS (Analog Ground)

ADCinput var WORD

OldADC0 var WORD
OldADC3 var WORD
NewADC0 var WORD
NewADC3 var WORD
ADCshift var WORD

Pause 100 ' Let PIC and LCD stabilize
ADCinput = 0
OldADC0 = 9999 : OldADC3 = 9999
NewADC0 = 0 : NewADC3 = 0

LCDOUT $FE, 1 : Pauseus 1
LCDOUT $FE, $80, " ADC test" : Pauseus 1
LCDOUT $FE, $94, "ADC0:" : Pauseus 1
LCDOUT $FE, $D4, "ADC3:" : Pauseus 1

Mainloop:

rem ADC 0

ADPCH = AVSS : adcin 0, ADCinput
NewADC0 = 1023 - ADCinput ' inverted so pot goes from 0 to 1024

if NewADC0 <> oldadc0 then
oldadc0 = NewADC0
ADCshift = NewADC0 / 4
LCDOUT $FE, $94+6, DEC4 oldadc0, " ", dec4 ADCshift : Pauseus 1
endif


rem ADC 3

ADPCH = AVSS : adcin 3, ADCinput
NewADC3 = ADCinput

if NewADC3 <> oldadc3 then
oldadc3 = NewADC3
ADCshift = NewADC3 / 4
LCDOUT $FE, $D4+6, DEC4 oldadc3, " ", dec4 ADCshift : Pauseus 1
endif

GOTO Mainloop
end

It still jitters. I'm sure I'm missing some parameters.

[Demon]

Can't edit my post:

(like changing from 4V down to 1V)

And of course my code alignment is totally whacked...

[Demon]

if your scope probes are ac coupled to measure rail noise [ as they should be ] then the DC offsets visible on the scope are not coming from your circuit the scope provides them , the drift you see is random, for stability each and every scope probe gnd reference lead needs to be connected to the same point


ps warning , do not try to measure rails that don't share a common gnd reference , or exceed the scopes safe working voltage

Ok.


All rails come from the same source; 5VDC.

And they all share the ground to that circuit.

[Demon]

Added DEFINE and doubled the ADCIN, no change really.

But I did notice a vulnerability in my system. Watch this when I gently touch power leads to the rails.

[richard]

the problem you see does not exist , its the scopes reaction to having an large antenna [YOUR HAND] capacitively coupled to all of its inputs providing an overwhelming signal on it most sensitive ac input range, the scope is unable to provide the dc bias needed to keep the traces aligned in the overwhelmed state

[Demon]

the problem you see does not exist , its the scopes reaction to having an large antenna [YOUR HAND] capacitively coupled to all of its inputs providing an overwhelming signal on it most sensitive ac input range, the scope is unable to provide the dc bias needed to keep the traces aligned in the overwhelmed state

Excellent, so this won't be an issue since the drop-down circuit will be linked directly the the main board by headers.

[richard]

I try to keep my development code as close to final as possible, cause I know I'll forget to change stuff back. At least this way I can fire and forget the pin initialization

.


grounding unused pins and setting them as outputs is pointless , useless and potentially catastrophic


just leaving them as analog is ten times easier and can never do any harm, setting them as input with wpu on is also ok and can never do any harm

if the device is not battery powered its not worth any sort of effort

[Demon]

- digital input,
- weak pull-up ON,
- pin not connected.

I try to stay away from analog settings; no idea why. Maybe cause I started using only digital way back when.

https://skills.microchip.com/introdu...tecture/691929

Unit will always be powered by wall adapter, or possibly USB; but never battery..

[Demon]

According to this:

https://skills.microchip.com/introdu...tecture/691929

The pull-up is disabled automatically when either TRIS is set to an output or the pin is set as an analog input. These changes to TRIS and ANSEL will override WPU settings.

I can just set all pull-ups ON, leave the unused pins unconnected and forget about them. Then use the others as I wish in ANSEL and TRIS.

The only times I need to be concerned with WPU is on pins that must not be disturbed for whatever special reason.

WPUA = %11111111    '----------------------------------------------------------------'
WPUB = %11111111    '           ALWAYS SET WEAK PULL-UPS ON ALL PINS FIRST           '
WPUC = %11111111    '----------------------------------------------------------------'
                    '       CHANGES TO ANSEL AND TRIS WILL OVERRIDE AS REQUIRED      '
                    '----------------------------------------------------------------'

ANSELA = %00000010                      ' Pin A3 = SW input                 not implemented yet
                                        ' Pin A2 = ADC (B5K)                not implemented yet
                                        ' Pin A1 = ADC (B5K)
                                        ' Pin A0 = ADC (voltage divider)    not implemented yet
ANSELB = %00000000
ANSELC = %00000000

TRISA = %00000010                       ' Pin A3 = SW input                 not implemented yet
                                        ' Pin A2 = ADC input 2              not implemented yet
                                        ' Pin A1 = ADC input 1
                                        ' Pin A0 = ADC input 0              not implemented yet
TRISB = %00000000                       ' Pin B7 = ...not available, ICSPDAT
                                        ' Pin B6 = ...not available, ICSPCLK
TRISC = %11000000                       ' Pin C7 = RX      *** Datasheet requirement, INPUT ***
                                        ' Pin C6 = TX      *** Datasheet requirement, INPUT ***

EDIT: I can even leave PORT at the top in case a pin is left as analog output.

PORTA = %00000000                       '-------------------------------------------' 
PORTB = %00000000                       '       ALWAYS SET PINS LOW FIRST           '
PORTC = %00000000                       '-------------------------------------------'

Or did I miss something important...?

[richard]

making any measurements on a dc signal other than the ac noise level using a scope that is ac coupled to the dc signal is meaningless

[Ioannis]

All your setup is on a Breadboard?

I can suspect that even low current PWM loads on a breadboard may cause such issues. The stray capacitance of these things is too mauch to have a reliable operation.

My test of ADC on a Picdem boards show rock-solid readings. But is of good design with a lot of grounds that you are missing on breadboards.

Ioannis