Originally Posted by
Aussie Barry
I would try the following:
1/. Use the Fixed Voltage Reference (FVR) instead of Vdd as your ADC reference voltage.
2/. Add some capacitance - say 100nF - between the pot wiper and ground.
Cheers
Barry
VK2XBP
Ok, finally got back to working on my ADC jitters:
- FOSC/128, 111111, 4.0 uS at 32 MHz
- using FVR x 4
- added 0.1uF at ADC pin
No change, still jitters. I took at the manual averaging routine; it doesn't go to the extreme ends (rarely get completely to 0 or 1024 because of jittter).
I'd like to try one of those COMPUTATION FEATURES, but I'm not sure which is better for me, nor what I need to properly set in the registers:
- Basic: essentially what I'm doing now.
- Accumulate,
- Average,
- Burst Average,
- Low-Pass Filter.
I'm testing 2 pots on this board; 1 regular, 1 with switch.
Code:
#CONFIG
__config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_ON
__config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
__config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_OFF & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
__config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF
__config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG
DEFINE OSC 32
DEFINE ADC_BITS 10 ' 10-bit Analog to digital
DEFINE LCD_DREG PORTB ' Set LCD data port
DEFINE LCD_DBIT 0 ' Set starting data bit
DEFINE LCD_RSREG PORTC ' Set LCD register select port
DEFINE LCD_RSBIT 4 ' Set LCD register select bit
DEFINE LCD_EREG PORTC ' Set LCD enable port
DEFINE LCD_EBIT 5 ' Set LCD enable bit
DEFINE LCD_BITS 4 ' Set LCD bus size
DEFINE LCD_LINES 4 ' Set number of lines on LCD
DEFINE LCD_COMMANDUS 1000 ' Set command delay time in microseconds
DEFINE LCD_DATAUS 50 ' Set data delay time in microseconds
define CCP1_REG 0 ' Must clear unused CCP pins or else unpredictable results
DEFINE CCP1_BIT 0
define CCP2_REG 0
DEFINE CCP2_BIT 0
define CCP3_REG PORTB ' PWM Pulse out to LCD backlight
DEFINE CCP3_BIT 5
define CCP4_REG 0 ' Must clear unused CCP pins or else unpredictable results
DEFINE CCP4_BIT 0
define CCP5_REG 0
DEFINE CCP5_BIT 0
FVRCON = %10000011 ' FIXED VOLTAGE REFERENCE CONTROL REGISTER
' bit 7 FVREN: Fixed Voltage Reference Enable bit
' ---> 1 = Fixed Voltage Reference is enabled
' 0 = Fixed Voltage Reference is disabled
' bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
' 1 = Fixed Voltage Reference output is ready for use
' 0 = Fixed Voltage Reference output is not ready or not enabled
' bit 5 TSEN: Temperature Indicator Enable bit(3)
' 1 = Temperature Indicator is enabled
' 0 = Temperature Indicator is disabled
' bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
' 1 = VOUT = VDD - 4VT (High Range)
' 0 = VOUT = VDD - 2VT (Low Range)
' bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
' 11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2)
' 10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2)
' 01 = Comparator FVR Buffer Gain is 1x, (1.024V)
' 00 = Comparator FVR Buffer is off
' bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
' ---> 11 = ADC FVR Buffer Gain is 4x, (4.096V)(2)
' 10 = ADC FVR Buffer Gain is 2x, (2.048V)(2)
' 01 = ADC FVR Buffer Gain is 1x, (1.024V)
' 00 = ADC FVR Buffer is off
'
' Note 1: FVRRDY is always ‘1’ for PIC16F18855/75 devices only.
' 2: Fixed Voltage Reference output cannot exceed VDD.
CCP3CON = %10001111 ' CCP3 CONTROL REGISTER
' bit 7 EN: CCPx Module Enable bit
' 1 = CCPx is enabled
' 0 = CCPx is disabled
' bit 6 Unimplemented: Read as ‘0’
' bit 5 OUT: CCP3 Output Data bit (read-only)
' bit 4 FMT: CCPW (Pulse Width) Alignment bit
' MODE = Capture mode
' Unused
' MODE = Compare mode
' Unused
' MODE = PWM mode
' 1 = Left-aligned format
' 0 = Right-aligned format
' bit 3-0 MODE<3:0>: CCPx Mode Select bits(1)
' ---> 1111 = PWM mode
' 1110 = Reserved
' 1101 = Reserved
' 1100 = Reserved
' 1011 = Compare mode: output will pulse 0-1-0; Clears TMR1
' 1010 = Compare mode: output will pulse 0-1-0
' 1001 = Compare mode: clear output on compare match
' 1000 = Compare mode: set output on compare match
' 0111 = Capture mode: every 16th rising edge of CCPx input
' 0110 = Capture mode: every 4th rising edge of CCPx input
' 0101 = Capture mode: every rising edge of CCPx input
' 0100 = Capture mode: every falling edge of CCPx input
' 0011 = Capture mode: every edge of CCPx input
' 0010 = Compare mode: toggle output on match
' 0001 = Compare mode: toggle output on match; clear TMR1
' 0000 = Capture/Compare/PWM off (resets CCPx module)
ADCON0 = %10000100 ' ADC CONTROL REGISTER 0
' bit 7 ADON: ADC Enable bit
' ---> 1 = ADC is enabled
' 0 = ADC is disabled
' bit 6 ADCONT: ADC Continuous Operation Enable bit
' 1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is
' set) or until ADGO is cleared (regardless of the value of ADSOI)
' ---> 0 = ADGO is cleared upon completion of each conversion trigger
' bit 5 Unimplemented: Read as ‘0’
' bit 4 ADCS: ADC Clock Selection bit
' 1 = Clock supplied from FRC dedicated oscillator
' ---> 0 = Clock supplied by FOSC, divided according to ADCLK register
' bit 3 Unimplemented: Read as ‘0’
' bit 2 ADFRM0: ADC results Format/alignment Selection
' ---> 1 = ADRES and ADPREV data are right-justified
' 0 = ADRES and ADPREV data are left-justified, zero-filled
' bit 1 Unimplemented: Read as ‘0’
' bit 0 ADGO: ADC Conversion Status bit
' 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is
' cleared by hardware as determined by the ADCONT bit
' ---> 0 = ADC conversion completed/not in progress
ADCLK = %00111111 ' ADC CLOCK SELECTION REGISTER
' bit 7-6 Unimplemented: Read as ‘0’
' bit 5-0 ADCCS<5:0>: ADC Conversion Clock Select bits
' ---> 111111 = FOSC/128
' 111110 = FOSC/126
' 111101 = FOSC/124
' •
' 000000 = FOSC/2
ADPCH = %00000000 ' ADC POSITIVE CHANNEL SELECTION REGISTER
' bit 7-6 Unimplemented: Read as ‘0’
' bit 5-0 ADPCH<5:0>: ADC Positive Input Channel Selection bits
' 111111 = Fixed Voltage Reference (FVR)
' 111110 = DAC1 output
' 111101 = Temperature Indicator
' 111100 = AVSS (Analog Ground)
' 111011 = Reserved. No channel connected.
' •
' •
' •
' 100010 = ANE2 * 16F18877 only
' 100001 = ANE1 * 16F18877 only
' 100000 = ANE0 * 16F18877 only
' 011111 = AND7 * 16F18877 only
' 011110 = AND6 * 16F18877 only
' 011101 = AND5 * 16F18877 only
' 011100 = AND4 * 16F18877 only
' 011011 = AND3 * 16F18877 only
' 011010 = AND2 * 16F18877 only
' 011001 = AND1 * 16F18877 only
' 011000 = AND0 * 16F18877 only
' 010111 = ANC7
' 010110 = ANC6
' 010101 = ANC5
' 010100 = ANC4
' 010011 = ANC3
' 010010 = ANC2
' 010001 = ANC1
' 010000 = ANC0
' 001111 = ANB7
' 001110 = ANB6
' 001101 = ANB5
' 001100 = ANB4
' 001011 = ANB3
' 001010 = ANB2
' 001001 = ANB1
' 001000 = ANB0
' 000111 = ANA7
' 000110 = ANA6
' 000101 = ANA5
' 000100 = ANA4
' 000011 = ANA3
' 000010 = ANA2
' ---> 000001 = ANA1
' ---> 000000 = ANA0
ANSELA = %00000011 ' Pin A1 = ADC
' Pin A0 = ADC
ANSELB = %00000000
ANSELC = %00000000
TRISA = %00000111 ' Pin A2 = SW input 1
' Pin A1 = ADC input 1
' Pin A0 = ADC input 0
TRISB = %00000000
TRISC = %00000000
SW1 var PORTA.2
ADCinput var WORD
OldADC0 var WORD
OldADC1 var WORD
OldSW1 var BYTE
NewADC0 var WORD
NewADC1 var WORD
HPWMbacklight var BYTE
' Pause 200 ' Let PIC and LCD stabilize
ADCinput = 0
OldADC0 = 9999
OldADC1 = 9999
OldSW1 = 9
NewADC0 = 0
NewADC1 = 0
HPWMbacklight = 150
HPWM 3,HPWMbacklight,1953
LCDOUT $FE, 1 : Pauseus 1
LCDOUT $FE, $80, " ADC test" : Pauseus 1
LCDOUT $FE, $94, "ADC 0:" : Pauseus 1
LCDOUT $FE, $D4, "ADC 1: SW:" : Pauseus 1
Mainloop:
rem ADC 0
ADPCH = %00000000
adcin 0, ADCinput
NewADC0 = 1023 - ADCinput
if NewADC0 <> oldadc0 then
oldadc0 = NewADC0
LCDOUT $FE, $94+7, DEC4 oldadc0 : Pauseus 1
endif
rem ADC 1
ADPCH = %00000001
adcin 1, ADCinput
NewADC1 = 1023 - ADCinput
if NewADC1 <> oldadc1 then
oldadc1 = NewADC1
LCDOUT $FE, $D4+7, DEC4 oldadc1 : Pauseus 1
endif
rem SW 1
if SW1 <> oldSW1 then
oldSW1 = SW1
IF OldSW1 = 0 THEN
LCDOUT $FE, $D4+17, "Off" : Pauseus 1
else
LCDOUT $FE, $D4+17, "On " : Pauseus 1
endif
endif
HPWMbacklight = 255 - (NewADC0 / 4)
HPWM 3,HPWMbacklight,1953
GOTO Mainloop
end
Re: How can I reduce ADC drift
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