This approach is often used as a voltage reference, but rarely as a power supply because it's very inefficient and has lots of other issues. You need to size the resistor so the voltage across it does not cause a troublesome dip in the VDD voltage at peak currents. Typically, you would need to have about 10x the current the PIC needs flowing all the time in the zener. A much more robust approach would be to put this circuit to the base of a NPN transistor, with the collector on the supply rail and the emitter on VDD. Then you can reduce the quiescent current consumed by roughly the gain of the transistor.
Anyway, this circuit is fine for a demo or an application where there's lots of free current. Of course, every time the PIC takes a sip of current, noise is induced on VDD. Maybe it doesn't matter - but anything with an ADC using VDD as reference won't be happy. Note it will have a much better sense of humour with a big cap across the zener for those computational gulps of current. Of course, then it will come up slowly, which might cause other issues. In the end, a 3 terminal regulator is the easiest, and may even be the cheapest solution.
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