My TMR1_INT Blinky is not blinking

[richard]

dt ints will not enable intcon PEIE you need to

yes with the newer chips some interrupt enable bits and flags have been relocated from INTCON reg into PIEx/PIRx regs
I'm not convinced dt-ints14 will always set the PEIE bit in INTCON when needed in all cases so i do it manually.
to set PEIE WITH GIE use
INTCON=$C0



for this chip and timer1 interrupts its not necessary dt-ints will set PEIE for you but this has no relationship with PIE4.0, i have no idea how you made that inference



just how does PIE4.0 = 0 stop the timer ?

writing to the timer like this when its still running is a very bad idea
TMR1H = 60 : TMR1L = 176 ' 50msec interval (32MHz, 16bit, 1:8)

[Demon]

...for this chip and timer1 interrupts its not necessary dt-ints will set PEIE for you but this has no relationship with PIE4.0, i have no idea how you made that inference...

I think I got that originally from the datasheet:
(16F18877 p.138)

Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.

It looks to me like INTCOM is a master breaker; shutting that down shuts all interrupts.

And individual interrupts can be managed via their PIE registers (ie: PIE4 alone manages 6 timers)

[Demon]

...just how does PIE4.0 = 0 stop the timer ?...

(also p.138)

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Enables the Timer1 overflow interrupt

[richard]

pic16 's have one level of interrupt , therefore an interrupt can never be interrupted

disabling the timer1 interrupt inside an interrupt is a pointless exercises that accomplishes exactly nothing
except to waste machine cycles

disabling the timer1 interrupt does not in any way shape or form stop the timer from running.

the only way to stop the timer is to either turn it off or stop its clock signal.

[Demon]

pic16 's have one level of interrupt , therefore an interrupt can never be interrupted ...

No, but any interrupt triggered while an ISR is running will be handled once the ISR finishes.

(p.129 16F18877)

Note

1: Individual interrupt flag bits are set, regardless of the state of any other enable bits.

2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

So you can have multiple Timers running at the same time (including USART interrupts and others).

No...?

[richard]

So you can have multiple Timers running at the same time (including USART interrupts and others).

of course you can, as many enabled as you see fit

but one and only one can be serviced at a time, and it cannot be interrupted. first come first served.
additional interrupts are serviced sequentially, one and only one at a time in the order the interrupt handler runs them.
hence keep isr's short