My TMR1_INT Blinky is not blinking

[Demon]

internal osc, what is the error %...... xtal osc matches with multicalc calculations

High-Precision Internal Oscillator:

- Software selectable frequency range up to 32 MHz, ±1% typical

I hadn't thought of that.

[richard]

Lets have a look at this

ToggleLED1:
    PIE4.0 = 0                                  ' Stops Timer1  no it dosent
    TOGGLE PortB.4
    T1CON.0 = 0                                 ' Resets Timer1 gate no it dosent
    T1CON.0 = 1
    TMR1H = 2 : TMR1L = 24
'    TMR1H = 4 : TMR1L = 161
    PIE4.0 = 1                                  ' Restarts Timer1 no it dosent
@ INT_RETURN

should be more like

ToggleLED1:
    T1CON.0 = 0                                   ' Stops Timer1     
    TMR1H = 2 : TMR1L = 18
    T1CON.0 = 1                        ' Restarts Timer1
    TOGGLE PortB.4 
@ INT_RETURN

[richard]

to get 65ms from my chip
TMR1H = 0 : TMR1L = 18
is required, so the int osc is not all that accurate
with multicalc figure i get about 64.8mS

[Demon]

...PIE4.0 = 1 ' Restarts Timer1 no it dosent...

Now I'm confused. I thought you said I had to handle it?

... dt ints will not enable intcon PEIE you need to

This runs 50msec non-stop:

#CONFIG
    __config _CONFIG1, _FEXTOSC_OFF & _RSTOSC_HFINT32 & _CLKOUTEN_OFF & _CSWEN_OFF & _FCMEN_ON
    __config _CONFIG2, _MCLRE_ON & _PWRTE_OFF & _LPBOREN_OFF & _BOREN_ON & _BORV_LO & _ZCD_OFF & _PPS1WAY_OFF & _STVREN_ON & _DEBUG_OFF
    __config _CONFIG3, _WDTCPS_WDTCPS_11 & _WDTE_OFF & _WDTCWS_WDTCWS_7 & _WDTCCS_LFINTOSC
    __config _CONFIG4, _WRT_OFF & _SCANE_available & _LVP_OFF
    __config _CONFIG5, _CP_OFF & _CPD_OFF
#ENDCONFIG

include "I:\Project_v2\PBP\PBP_Includes\DT_INTS-14_16F18877.bas"
include "I:\Project_v2\PBP\PBP_Includes\ReEnterPBP.bas"
ASM
INT_LIST  macro    ; IntSource,        Label,  Type, ResetFlag?
        INT_Handler    TMR1_INT,  _ToggleLED1,   PBP,  yes
    endm
    INT_CREATE               ; Creates the interrupt processor
ENDASM

DEFINE OSC 32
ANSELA = %00000000
ANSELB = %00000000
ANSELC = %00000000
ANSELD = %00000000
ANSELE = %00000000
TRISA = %00000000                       
TRISB = %00000000                       
TRISC = %00000000                         
TRISD = %00000000                        
TRISE = %00000000

T1CON = %00110001                                   ' 1:8 Prescale, Enables Timer1
'   bit 7-6 Unimplemented: Read as ‘0’
'   bit 5-4 CKPS<1:0>: Timer1 Input Clock Prescale Select bits
'        ---->  11 = 1:8 Prescale value
'               10 = 1:4 Prescale value
'               01 = 1:2 Prescale value
'               00 = 1:1 Prescale value
'   bit 3   Unimplemented: Read as ‘0’
'   bit 2   SYNC: Timer1 Synchronization Control bit
'                   When TMR1CLK = FOSC or FOSC/4
'                       This bit is ignored. The timer uses the internal clock and no
'                       additional synchronization is performed.
'                   When TMR1CS<1:0> = (any setting other than FOSC or FOSC/4)
'               1 = Do not synchronize external clock input
'               0 = Synchronized external clock input with system clock
'   bit 1   RD16: Timer1 On bit
'               1 = All 16 bits of Timer1 can be read simultaneously (TMR1H is buffered)
'               0 = 16-bit reads of Timer1 are disabled (TMR1H is not buffered)
'   bit 0   ON: Timer1 On bit
'        ---->  1 = Enables Timer1
'               0 = Stops Timer1 and clears Timer1 gate flip-flop

T1CLK = %00000001                                   ' FOSC/4 Timer1 Clock
'   bit 7-4 Unimplemented: Read as ‘0’
'   bit 3-0 TxCS<3:0>: Timer1/3/5 Clock Select bits
'               1111 = LC4_out
'               1110 = LC3_out
'               1101 = LC2_out
'               1100 = LC1_out
'               1011 = TMR5 overflow output(3)
'               1010 = TMR3 overflow output(2)
'               1001 = TMR1 overflow output(1)
'               1000 = TMR0 overflow output
'               0111 = CLKR output clock
'               0110 = SOSC
'               0101 = MFINTOSC                     ' 1.05msec @ 32MHz with no preload
'               0100 = LFINTOSC                     ' n/a
'               0011 = HFINTOSC                     ' 16.56msec @ 32MHz with no preload
'               0010 = FOSC                         ' 16.54msec @ 32MHz with no preload
'        ---->  0001 = FOSC/4                       ' 66.18msec @ 32MHz with no preload
'               0000 = TxCKIPPS
    
                                LatB.0 = 0
    TMR1H = 60 : TMR1L = 176                    ' 50msec interval (32MHz, 16bit, 1:8)
    PIE4.0 = 1                                  ' Starts Timer1
                                LatB.0 = 1

Main:
    LatB.5 = 1                              ' Heartbeat
    LatB.5 = 0
GOTO Main

ToggleLED1:
                                LatB.0 = 0
'    PIE4.0 = 0                                  ' Stops Timer1
    TMR1H = 60 : TMR1L = 176                    ' 50msec interval (32MHz, 16bit, 1:8)
'    PIE4.0 = 1                                  ' Restarts Timer1
                                LatB.0 = 1
@ INT_RETURN

This starts it once (same defines and registers):

ToggleLED1:
                                LatB.0 = 0
    PIE4.0 = 0                                  ' Stops Timer1
    TMR1H = 60 : TMR1L = 176                    ' 50msec interval (32MHz, 16bit, 1:8)
'    PIE4.0 = 1                                  ' Restarts Timer1
                                LatB.0 = 1
@ INT_RETURN

This stops it, then starts it back up again (this is what I need for my project):

ToggleLED1:
                                LatB.0 = 0
    PIE4.0 = 0                                  ' Stops Timer1
    TMR1H = 60 : TMR1L = 176                    ' 50msec interval (32MHz, 16bit, 1:8)
    PIE4.0 = 1                                  ' Restarts Timer1
                                LatB.0 = 1
@ INT_RETURN

[richard]

dt ints will not enable intcon PEIE you need to

yes with the newer chips some interrupt enable bits and flags have been relocated from INTCON reg into PIEx/PIRx regs
I'm not convinced dt-ints14 will always set the PEIE bit in INTCON when needed in all cases so i do it manually.
to set PEIE WITH GIE use
INTCON=$C0



for this chip and timer1 interrupts its not necessary dt-ints will set PEIE for you but this has no relationship with PIE4.0, i have no idea how you made that inference



just how does PIE4.0 = 0 stop the timer ?

writing to the timer like this when its still running is a very bad idea
TMR1H = 60 : TMR1L = 176 ' 50msec interval (32MHz, 16bit, 1:8)

[Demon]

...for this chip and timer1 interrupts its not necessary dt-ints will set PEIE for you but this has no relationship with PIE4.0, i have no idea how you made that inference...

I think I got that originally from the datasheet:
(16F18877 p.138)

Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.

It looks to me like INTCOM is a master breaker; shutting that down shuts all interrupts.

And individual interrupts can be managed via their PIE registers (ie: PIE4 alone manages 6 timers)

[Demon]

...just how does PIE4.0 = 0 stop the timer ?...

(also p.138)

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Enables the Timer1 overflow interrupt

[richard]

pic16 's have one level of interrupt , therefore an interrupt can never be interrupted

disabling the timer1 interrupt inside an interrupt is a pointless exercises that accomplishes exactly nothing
except to waste machine cycles

disabling the timer1 interrupt does not in any way shape or form stop the timer from running.

the only way to stop the timer is to either turn it off or stop its clock signal.

[Demon]

pic16 's have one level of interrupt , therefore an interrupt can never be interrupted ...

No, but any interrupt triggered while an ISR is running will be handled once the ISR finishes.

(p.129 16F18877)

Note

1: Individual interrupt flag bits are set, regardless of the state of any other enable bits.

2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

So you can have multiple Timers running at the same time (including USART interrupts and others).

No...?