Help configuring 2 CCP interupts

[richard]

pic chips have only one interrupt vector

DEFINE INTHAND CCP_INT ' Declare high-pri interrupt handler

needs to do something like this

DEFINE INTHAND which_CCP_INT ' Declare high-pri interrupt handler



then

asm
which_ccp_int

pseudo code wise
if ccp1 INTflag set then bra ccp_int1
else
if ccp2 INTflag set then bra ccp_int2
else
RETFIE FAST ' not my interrupt

CCP_INT1
BTFSS CCP1CON,0 ; capture from rising edge?
BRA Fall ; no .. goto falling edge
MOVFF CCPR1L, _T1 ; get low capture byte into _T1
MOVFF CCPR1H, _T1+1 ; get high capture byte into _T1
BRA IntExit ; outta here
Fall
MOVFF CCPR1L, PW ; get low capture byte into PW
MOVFF CCPR1H, PW+1 ; get high capture byte into PW
BSF CF,0 ; indicate last capture
IntExit
BTG CCP1CON,0 ; toggle between rising/falling edge captures
BCF PIR1,2 ; clear capture interrupt flag bit
RETFIE FAST ; return/restore W, STATUS and BSR

CCP2_INT
BTFSS CCP2CON,0 ; capture from rising edge?
BRA Fall2 ; no .. goto falling edge
MOVFF CCPR2L, _T2 ; get low capture byte into _T1
MOVFF CCPR2H, _T2+1 ; get high capture byte into _T1
BRA IntExit2 ; outta here
Fall2
MOVFF CCPR2L, PW2 ; get low capture byte into PW
MOVFF CCPR2H, PW2+1 ; get high capture byte into PW
BSF CF2,0 ; indicate last capture
IntExit2
BTG CCP2CON,0 ; toggle between rising/falling edge captures
BCF PIR2,0 ; clear capture interrupt flag bit
RETFIE FAST ; return/restore W, STATUS and BSR

ENDASM

[spcw1234]

Thank you! That helped me get it working

[HenrikOlsson]

> pic chips have only one interrupt vector
Yes and no. 18F-series chips have two, one high priority (0x0008h) and one low pritority (0x0018h) and the DEFINE's, as they were written in ONE of the code examples posted was defining one handler for the high priority and one for the low. However, both handlers had RETFIE FAST at the end which, to me, seems like a mistake if there's any possibillity of a high priroty interrupt tripping while a low priority interrupt is executing. It may be why they worked on their own but not both at the same time.

Anyway, if you got it working then none of it really matters.

/Henrik.

[richard]

it should also be noted that for a low priority int handler

wsave,ssave,bsave vars are required to save and restore chips status on entry/exit

and that the chosen int priority must match settings

DEFINE INTHAND CCP_INT ' Declare high-pri interrupt handler
DEFINE INTLHAND CCP2_INT ' Declare interrupt handler


CapPriEn = 1 'Set CCP1 int to high priority
CapPriEn2 = 0 'Set CCP2 int to low priority

also to note that none or the isr's in this thread have made any attempt at ensuring correct banksel
a few chk??rp lines would make things more reliable

[spcw1234]

Below is my working ASM interrupt routine. I'm sure it could be improved, but it appears to work 100%. Using only 1 priority interrupt for the CCP module. Thanks for all the help!

ASM
X_CCP_INT
  BTFSC PIR1,2          ; if ccp1
  BRA CCP_INT           ; goto CCP_INT
  BTFSC PIR2,0          ; if ccp2
  BRA CCP2_INT          ; goto CCP2_INT
  RETFIE FAST           ; outta here 
CCP_INT
  BTFSS CCP1CON,0       ; capture from rising edge?
  BRA Fall              ; no .. goto falling edge
  MOVFF CCPR1L, _T1     ; get low capture byte into _T1
  MOVFF CCPR1H, _T1+1   ; get high capture byte into _T1
  BRA IntExit           ; outta here
Fall
  MOVFF CCPR1L, PW      ; get low capture byte into PW
  MOVFF CCPR1H, PW+1    ; get high capture byte into PW
  BSF CF,0              ; indicate last capture
IntExit
  BTG CCP1CON,0         ; toggle between rising/falling edge captures
  BCF PIR1,2            ; clear capture interrupt flag bit
  RETFIE FAST           ; return/restore W, STATUS and BSR
CCP2_INT
  BTFSS CCP2CON,0       ; capture from rising edge?
  BRA Fall2             ; no .. goto falling edge
  MOVFF CCPR2L, _T2     ; get low capture byte into _T1
  MOVFF CCPR2H, _T2+1   ; get high capture byte into _T1
  BRA IntExit2          ; outta here
Fall2
  MOVFF CCPR2L, PW2     ; get low capture byte into PW
  MOVFF CCPR2H, PW2+1   ; get high capture byte into PW
  BSF CF2,0             ; indicate last capture
IntExit2
  BTG CCP2CON,0         ; toggle between rising/falling edge captures
  BCF PIR2,0            ; clear capture interrupt flag bit
  RETFIE FAST           ; return/restore W, STATUS and BSR
ENDASM

[Archangel]

pic chips have only one interrupt vector

This one statement solved a problem I was having.
So I combined my ISRs into one and Viola',
Thanks Richard