Quote Originally Posted by BH_epuk View Post
Chris
A thought accured to me RE timer 3. did you check the configuration bits in CONFIG3H?

bit 4 T3CMX: Timer3 Clock Input MUX bit
1 = T3CKI is on RC0
0 = T3CKI is on RB5


MOUNTAIN747
I'm not sure that could be the cause given the unreliability of the fault. If set up incorrectly it would work consistently poorly. As it is, the 1 second epoch is always on time (suggesting that the correct count of 32768 pulses from the crystal are being used).

The symptom is that sometimes in the ISR, the interrupt bit for the Timer 3 overflow interrupt doesn't clear when instructed to do so.

Normal operation is that the timer overflows, an interrut is generated, which is then services and cleared, and one second gets added to the Seconds counter.
Sometimes, the Seconds counter increments by two instead of one, suggesting that the ISR is called twice and the TMR3 interrupt is serviced twice for only one TMR3 overflow condition.