1Hz clock using Timer3, 32.768kHz crystal and runs badly on 18F26k22

[Chris Barron]

Good shout Henrik.

If it is any consolation Wayne you won't be the first or the last to be stumped in that way.

Now, if you ever find out why Timer 3 didn't behave the same as Timer 1 for me, feel free to let me know !

Chris

[MOUNTAIN747]

Chris, I'll let you know when I find out! I feel like a dummy for stumbling over that one. I am supprised MCSP would make that blunder when it was looking for MPLAB\MPASM. Oh Well, Automatic is not always Automatic...

[BH_epuk]

Chris
A thought accured to me RE timer 3. did you check the configuration bits in CONFIG3H?

bit 4 T3CMX: Timer3 Clock Input MUX bit
1 = T3CKI is on RC0
0 = T3CKI is on RB5


MOUNTAIN747

This is an example of config bit for the 18F2x/4xK22 devices based on PBP 2.60C


asm
__CONFIG _CONFIG1H, _FOSC_INTIO67_1H & _PLLCFG_OFF_1H & _PRICLKEN_ON_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
__CONFIG _CONFIG2L, _PWRTEN_ON_2L & _BOREN_OFF_2L & _BORV_285_2L
__CONFIG _CONFIG2H, _WDTEN_NOSLP_2H & _WDTPS_512_2H
__CONFIG _CONFIG3H, _CCP2MX_PORTC1_3H & _PBADEN_OFF_3H & _CCP3MX_PORTB5_3H & _HFOFST_OFF_3H & _T3CMX_PORTB5_3H & _P2BMX_PORTC0_3H & _MCLRE_EXTMCLR_3H
__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
__CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L
__CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H
__CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L
__CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H
__CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L
__CONFIG _CONFIG7H, _EBTRB_OFF_7H

ENDASM

You'll probably have to change to suit your application, but the above covers all the configs as a starter.
any Q's fell free to ask, I'm working on a project using the 44K22 at the moment so know the datasheet quite well.

[MOUNTAIN747]

BH_epuk, thanks for the update. I've just stated on the k22's data sheet. I know this is going to be a fun PIC to work with. AND, I may have some questions for you after I digest the next 300 pages!
Thanks
Wayne

[Chris Barron]

Chris
A thought accured to me RE timer 3. did you check the configuration bits in CONFIG3H?

bit 4 T3CMX: Timer3 Clock Input MUX bit
1 = T3CKI is on RC0
0 = T3CKI is on RB5


MOUNTAIN747

I'm not sure that could be the cause given the unreliability of the fault. If set up incorrectly it would work consistently poorly. As it is, the 1 second epoch is always on time (suggesting that the correct count of 32768 pulses from the crystal are being used).

The symptom is that sometimes in the ISR, the interrupt bit for the Timer 3 overflow interrupt doesn't clear when instructed to do so.

Normal operation is that the timer overflows, an interrut is generated, which is then services and cleared, and one second gets added to the Seconds counter.
Sometimes, the Seconds counter increments by two instead of one, suggesting that the ISR is called twice and the TMR3 interrupt is serviced twice for only one TMR3 overflow condition.

[Demon]

...Sometimes, the Seconds counter increments by two instead of one, suggesting that the ISR is called twice and the TMR3 interrupt is serviced twice for only one TMR3 overflow condition.

Totally off the top of my head; are you supposed to disable the interrupt handler as soon as you enter your interrupt routine and then re-enable it before leaving?

(I forgot assembler, 1983 is a long time away from now)

Robert