16F688 counter problem

[Bruce]

CMCON0 = 7 wouldn't hurt either..;o}

Edit: Note that PBP defaults to 4MHz. If you're using the internal 31kHz osc, expect pretty much all timing to be way off.

[Darrel Taylor]

CMCON0 = 7 wouldn't hurt either..;o}

Now how did I miss that?
I looked, didn't see comparators, DOH!

Nice catch Bruce.

[jderson]

I tried both suggestions, and it doesn't help. I am aware of the severe timing differences, but that shouldn't have anything to do with this, should it?

Thanks for your help.

[Darrel Taylor]

Here's another possibility.

By setting WDTCON = %0000000

If the config bit's say _WDT_ON then you can't turn off the Watch Dog Timer with the WDTCON.0

However, in the process, it's reduced the WDT prescaler to 1:32

Since the processor is running so slow. the WDT might not be getting cleared often enough.

So, either try turning off the WDT in the configs. Or set WDTCON = %00010110 (1:65536)

hth,

[jderson]

I changed it to WDTCON = %00010110, and it works! Thank you!

[Bruce]

Nice catch Darrel.

I would just set WDT_OFF with PBP assuming 4MHz, and running at 31kHz. Just in case. PBP will insert a NOP where it normally had a CLRWDT for timing, but there may be a library routine that doesn't hit the dog in time with the timing being so far out of whack.

[paul borgmeier]

Weird problem - just a comment

OPTION_REG defaults to $FF on power up. It looks like when you define the OPTION_REG value you are setting bits 4 and 5 but you are actually clearing bits 0-3 and 6-7. Bits 0-3 are harmless since they relate to the prescale of TMRO. Bit 6 sets the method of interrupt for RA2 - but the Interrupts are not enabled. That leaves Bit 7, which turns on the weak pull-ups. How strong of signal are you using to drive pin 11?

EDIT: a bit late but not the problem - glad it works