Determining trace/via/wire current capability

[Demon]

... For my taste your trace to via are too small(I know it is only signal, but...).

JLCPCB can support up to 0.15 vias. I'm using 0.3 hole/0.5 pad since I'm using 2 layer PCBs.

https://jlcpcb.com/capabilities/pcb-capabilities


I'm not finding any "ideal dimension" for signal traces on the web...? They seem unanimous to say "however small your PCB fabricator can handle".

I'm using:

- 0.2 traces default,
- 0.3 for USART/USB,
- 0.3 for VDD.

[Ioannis]

I'm not finding any "ideal dimension" for signal traces on the web...? They seem unanimous to say "however small your PCB fabricator can handle".

PCB design is a bit of art. So, rules do apply but you can bend them (within reason of course) using common sense.

Nice touch the cooled grounding. Never thought of that. Though I do not know how much will contribute in cooling if the main tab is big enough.

Ioannis

[pedja089]

Top is usualy bit tight with space, So I make GND al large as I can on bottom.
Uart usualy don't require any special routing. I usualy use trace width of smalest IC pad.
For USB it depends on lenght. It usualy doen't meter. But if it is long, it is critical to have diff pair with proper impedance....

[Demon]

...USB it depends on lenght. It usualy doen't meter. But if it is long, it is critical to have diff pair with proper impedance....

I read that people have been getting away with what they consider sloppy traces.

My USB traces are 20cm long, running side-by side, far from any large current. My application does not have to support USB 3.0, 2.0 is plenty fast for me.

[Demon]

... Nice touch the cooled grounding....

The vias in the VSS pin is not for cooling; it's just to get the current to the bottom side with more via conduit.

If I increase VSS via size, it messes up my spacing close to the TSSOP ICs.