Timer Interrupts

[gadelhas]

..........

Ok, steve, lets see, if my timer1 is low priority, and timer2 is high priority. The timer interrupts and starts to execute the code inside the ISR, meanwhile the timer2 triggers, since is high priority jumps to its own execution. What will hapen?
After the ISR of the timer2 finishs it jumps again to the ISR of the timer1 to the place where it was interrupt by timer2?

[SteveB]

Ok, steve, lets see, if my timer1 is low priority, and timer2 is high priority. The timer interrupts and starts to execute the code inside the ISR [low priority], meanwhile the timer2 triggers, since is high priority jumps to its own execution. What will hapen?

The next address that would be executed in the Low Priority ISR is pushed onto the stack and then the program branches to the location of the High Priority ISR (0008h), where it begins to execute that code.

After the ISR of the timer2 finishs it jumps again to the ISR of the timer1 to the place where it was interrupt by timer2?

Yes. It pulls the address off the stack and branches back to the low priority ISR.

It will also set the global enable bit for the High Priority interrupts, so that if another High Priority interrupt occurs, it will branch again to that ISR. (Which is why it is critical to reset the interrupt flags in the ISR)

Eventually, it should finish with the Low Priority ISR and branch back to the main program flow. (This will also set the global enable bit for Low Priority interrupts)

Clear as mud?

[SteveB]

One other thing.

You use the example of 2 timers, 1 HP and 1 LP. Keep in mind these could be any of the components capable of raising an interrupt, such as...
EUSART Receive Interrupt, CCP1 Interrupt, A/D Converter Interrupt, High/Low-Voltage Detect Interrupt, Etc.
Any of these can be enabled and set either to HP or LP. Also, more than one can be set to HP or LP.

Imagine you had two of them set to LP, and 1 to HP. A/D and HLVD set to LP. TMR1 to HP.
So the A/D triggers. Program jumps to LP ISR. While executing the LP ISR, the HLVD interrupt occurs. What happens?
The LP ISR just continues as if no other interrupt occured because the LP enable bit was cleared when it first entered the ISR. When the RETFIE command (return from interrupt command) is executed the LP enable bit is set again. Assuming the A/D flag was reset, but not the HLVD, the program would immediately branch back to the LP ISR again. In these cases, where you have more than one item that can raise an interrupt, the ISR needs to check which flag was set so it knows what to do.

Now, at ANY time (in this example), if the TMR1 interrupt occurs, it jumps to the HP ISR, executes the ISR, then jumps back.

Hope I didn't make things even more muddy.

[gadelhas]

Many thanks SteveB, i understood perfectly.

Thank you everyone!

[mister_e]

Hope I didn't make things even more muddy.

It's my job to do so

Nice explanation!