One other thing.
You use the example of 2 timers, 1 HP and 1 LP. Keep in mind these could be any of the components capable of raising an interrupt, such as...
EUSART Receive Interrupt, CCP1 Interrupt, A/D Converter Interrupt, High/Low-Voltage Detect Interrupt, Etc.
Any of these can be enabled and set either to HP or LP. Also, more than one can be set to HP or LP.
Imagine you had two of them set to LP, and 1 to HP. A/D and HLVD set to LP. TMR1 to HP.
So the A/D triggers. Program jumps to LP ISR. While executing the LP ISR, the HLVD interrupt occurs. What happens?
The LP ISR just continues as if no other interrupt occured because the LP enable bit was cleared when it first entered the ISR. When the RETFIE command (return from interrupt command) is executed the LP enable bit is set again. Assuming the A/D flag was reset, but not the HLVD, the program would immediately branch back to the LP ISR again. In these cases, where you have more than one item that can raise an interrupt, the ISR needs to check which flag was set so it knows what to do.
Now, at ANY time (in this example), if the TMR1 interrupt occurs, it jumps to the HP ISR, executes the ISR, then jumps back.
Hope I didn't make things even more muddy.
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