OSCON setting for 18F4520

[mackrackit]

DEFINE OSC 8
OSCCON=%01110000
or
DEFINE OSC 4
OSCCON=%01100000

OSCTUNE.6 = 1 'PLL 4x
does not do PLL. As far as I know PLL is not possible with the internal OSC.

The other OSCON bits leave at zero, they are for reading.

[rmteo]

.... As far as I know PLL is not possible with the internal OSC.

From the datasheet (DS39631A):

2.5.2 PLL AND INTOSC
The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock output
of up to 32 MHz.

2.6.4 PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the internal
oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output frequency
is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those internal
oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.