Pot jitters during ADC capture


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  1. #1
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    Default Re: Pot jitters during ADC capture

    Richard has good point regarding crappy source signal.

    As noted before, if the pot is so bad it will be very difficult to clean the signal.

    The r-c values depend on the signal frequency that they will filter. Your pot signal is really slow and needs big cap and resistor values, called time constant.

    Having big r-c values driving Adc is difficult so a buffer is needed.

    Ioannis
    Last edited by Ioannis; - 8th August 2024 at 11:59.

  2. #2
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    Default Re: Pot jitters during ADC capture

    robert states
    Tried shifting out low 4 bits.


    ...mostly stable
    that means the pot resistance must vary in leaps of over 160 ohms [assuming correct technique]
    no amount of lpf will be useful in getting stable readings from "fine" movements under those conditions
    Warning I'm not a teacher

  3. #3
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    Default Re: Pot jitters during ADC capture

    Well, yes. Tossing lower 4 bits of 10 total means clearly that the source signal is too bad to be useful. If Robert insist on using those pots, then based on the fact that the wiper moves slowly, he should have a really big time constant on the R-C network to compensate for the "noise". And then he should also add buffers with such high Pot and R-C values. All these add extra cost. Better chose a better pot and done with it.

    Ioannis

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