
Originally Posted by
richard
given that I-inh max for a SN7407 gate is 40uA and a pic output pin could drive more than 20 of them and still produce a clean TTL signal.
i cannot see that signal timing would even be a consideration. just what need does the pullup fulfill ?
Except from preventing the input pin on the SN7407 from floating, I don't see one for my application.
I don't really care about "precision timing"; I just trigger the MCLR reset on the Slave with a 10usec pause. I still have a pull-up downstream on the Slave PIC.
Code:
SlaveMCLR = 0
PauseUS 10
SlaveMCLR = 1
EDIT: I figured I'd read the instructions AFTER posting that reply. 
11.1 Layout Guidelines: ... All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
Promptly runs over to breadboard to pull down the other 5 unused inputs.
Bookmarks