16F688 counter problem

I am trying to use TMR0 as a counter, and eventally display the count on the LCD. I am also running with the 32khz. internal oscillator. The following program works fine:

TRISC = %000000
TRISA = %000100
OSCCON = %00000011
WDTCON = %0000000

Define LCD_DREG PORTC 'Set LCD data port
DEFINE LCD_DBIT 0 'Set LCD starting data bit
DEFINE LCD_RSREG PORTC 'Set LCD register select port
DEFINE LCD_RSBIT 4 'Set LCD register select bit
DEFINE LCD_EREG PORTA 'Set LCD enable port
DEFINE LCD_EBIT 1 'Set LCD enable bit
DEFINE LCD_BITS 4 'Set LCD bus size
DEFINE LCD_LINES 2 'Set LCD number of lines




Lcdout $fe, 1 ' Clear LCD screen
Lcdout "I Love" ' Display Hello

Lcdout $fe, $C0 ' Clear LCD screen
Lcdout "This"

end

When I add this line:

OPTION_REG = %00110000

It quits working.

Does anyone know why?

Thank you.

Well, I can't find a specific symptom that exactly matches your description.

But I have a feeling it has something to do with many of the pins being in Analog mode.

Try adding ...

Code:

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ANSEL = 0

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CMCON0 = 7 wouldn't hurt either..;o}

Edit: Note that PBP defaults to 4MHz. If you're using the internal 31kHz osc, expect pretty much all timing to be way off.

Quote:

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Originally Posted by Bruce

CMCON0 = 7 wouldn't hurt either..;o}

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Now how did I miss that? :o
I looked, didn't see comparators, DOH!

Nice catch Bruce.

I tried both suggestions, and it doesn't help. I am aware of the severe timing differences, but that shouldn't have anything to do with this, should it?

Thanks for your help.

Here's another possibility.

By setting WDTCON = %0000000

If the config bit's say _WDT_ON then you can't turn off the Watch Dog Timer with the WDTCON.0

However, in the process, it's reduced the WDT prescaler to 1:32

Since the processor is running so slow. the WDT might not be getting cleared often enough.

So, either try turning off the WDT in the configs. Or set WDTCON = %00010110 (1:65536)

hth,

I changed it to WDTCON = %00010110, and it works! Thank you!

Weird problem - just a comment

OPTION_REG defaults to $FF on power up. It looks like when you define the OPTION_REG value you are setting bits 4 and 5 but you are actually clearing bits 0-3 and 6-7. Bits 0-3 are harmless since they relate to the prescale of TMRO. Bit 6 sets the method of interrupt for RA2 - but the Interrupts are not enabled. That leaves Bit 7, which turns on the weak pull-ups. How strong of signal are you using to drive pin 11?

EDIT: a bit late but not the problem - glad it works

Nice catch Darrel.

I would just set WDT_OFF with PBP assuming 4MHz, and running at 31kHz. Just in case. PBP will insert a NOP where it normally had a CLRWDT for timing, but there may be a library routine that doesn't hit the dog in time with the timing being so far out of whack.