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I found these web pages to better design my PCBs.
Traces:
https://www.mclpcb.com/blog/pcb-trac...current-table/
Vias:
https://www.worthingtonassembly.com/...hru-hole-sizes
Wires:
https://www.omnicalculator.com/physics/wire-size
EDIT:
Here's a calculator for traces/current:
https://circuitcalculator.com/wordpress/?p=25/
Valuable source of info.
Thanks for sharing,
Ioannis
If you want to increase trace/via capacity without increasing their size (maybe it complicates the rest of your circuit), just make more.
https://i.imgur.com/DH51l19.png
In my case, the 7805 voltage regulator takes the brunt of all components downstream, so that's where I increased their number.
Put vias under component. Make bottom copeer pad large, and you have much better heatsink capabilites.
Make via also untinted ut botom, so you can fill it with solder. For my taste your trace to via are too small(I know it is only signal, but...).
Attachment 9696
I understand that you use Eagle.
How can you prevent solder mask at the area of the VIAS under the smd component?
Ioannis
Yes it is eagle...
Attachment 9697
Also, you can draw any shape on that layer, and solder mask will be removed from that area.
Great!
Thank you,
Ioannis
How is this?Quote:
Originally Posted by pedja089
:)
https://i.imgur.com/ciQxPW1.png
I went one further using vias after adding cooling; grounding the VSS pin on the voltage regulator with 3 large vias.
This way it doesn't mess up the smaller vias I have on signal traces and VSS pins on tiny SMD ICs.
CORRECTION:
These are labelled backwards. The 7805 uses the TO-263 package and the Hexfet uses D2Pak (in my project).
https://i.imgur.com/91lOIbs.png
Quote:
Originally Posted by pedja089
JLCPCB can support up to 0.15 vias. I'm using 0.3 hole/0.5 pad since I'm using 2 layer PCBs.
https://jlcpcb.com/capabilities/pcb-capabilities
I'm not finding any "ideal dimension" for signal traces on the web...? They seem unanimous to say "however small your PCB fabricator can handle".
I'm using:
- 0.2 traces default,
- 0.3 for USART/USB,
- 0.3 for VDD.
PCB design is a bit of art. So, rules do apply but you can bend them (within reason of course) using common sense.Quote:
Originally Posted by Demon
Nice touch the cooled grounding. Never thought of that. Though I do not know how much will contribute in cooling if the main tab is big enough.
Ioannis
Top is usualy bit tight with space, So I make GND al large as I can on bottom.
Uart usualy don't require any special routing. I usualy use trace width of smalest IC pad.
For USB it depends on lenght. It usualy doen't meter. But if it is long, it is critical to have diff pair with proper impedance....
Quote:
Originally Posted by Ioannis
The vias in the VSS pin is not for cooling; it's just to get the current to the bottom side with more via conduit.
If I increase VSS via size, it messes up my spacing close to the TSSOP ICs.
Quote:
Originally Posted by pedja089
I read that people have been getting away with what they consider sloppy traces.
My USB traces are 20cm long, running side-by side, far from any large current. My application does not have to support USB 3.0, 2.0 is plenty fast for me.