Quote Originally Posted by Bruce View Post
Try removing these defines and see if it works.

DEFINE HSER_ODD 0
DEFINE HSER_EVEN 0
That did the trick! I reran the test and checked out the entire table again and it's perfect! Wow, what a relief! Strange that removing the parity defines = 0 would cause it to work. I'm guessing that would be a very important tip for people to remember in the future.

I looked under the pdf for the 18LF4685 and it says "Parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit" I wonder if that means if a person did want parity they would set the parity define and calc & stuff the 9th data bit or would PBP do it for them? Well that I will investigate. For this project I don't need parity although I will have to figure out the CRC algorithm of the VFD

Thank you skimask for the suggestion about speed / electrical problems. I wondered if that might be my problem also as my circuit layout is on the crude side. Thankfully my waveforms at 190kb have nice flat tops and nice, sharp looking rise fall profiles.

Time to glue the hair back to my head, get a little sleep and then get on with the project.

Thanks a million Bruce!
Bob