HPWM Confusion in spec sheet

[lerameur]

Also,

the 7'th bit (ADFM) of the ADCON1 REGISTER identifies left and right justification. Although in the pic16f88 spec sheet, page 119, figure 12-4 (A/D result justification) the answer of left or right justification BOTH are in 10 bit length.

So why is it that when we put ADCON1 =%00000000 means Left justified results in 8 bits ??

[skimask]

Also,

the 7'th bit (ADFM) of the ADCON1 REGISTER identifies left and right justification. Although in the pic16f88 spec sheet, page 119, figure 12-4 (A/D result justification) the answer of left or right justification BOTH are in 10 bit length.

So why is it that when we put ADCON1 =%00000000 means Left justified results in 8 bits ??

The A/D result can go into the 16 bit combined register ADRESH and ADRESL.
10 bits of A/D go into 16 bits of result...
Left justify goes into the upper 10 bits, right justify goes into the lower 10 bits.
But if you're using the ADCIN command, and you've defined a byte as the result, the variable used in ADCIN will hold the upper byte of the result from the ADC, which if you have it right justified, won't work too well.
If you've defined a word as the result of the ADCIN, then the 10 bits of the AD result will go into that word, depending on where the justify bit is set.