still don't have solution!!!

[rmteo]

Can't see the 'scope trace here (server won't let the image thru)...
In the absense of any other information (PIC type, CCP or ECCP, not that it matters), I would guess 1Mhz...
8Mhz / 4 ( crystal vs. Fosc) = 2 Mhz, but still need another cycle to set and/or reset the outputs in the CCP module, hence 1Mhz. Again, don't have enough info, nor datasheets handy.

Amazing as it seems, you can generate a 2MHz PWM with an 8MHz clock. Not only that but you also get 2-bit resolution (4 duty cycles).

[skimask]

Amazing as it seems, you can generate a 2MHz PWM with an 8MHz clock. Not only that but you also get 2-bit resolution (4 duty cycles).

Using the 4xPLL is cheating!

[rmteo]

No PLL used, just 8MHz clock.

[skimask]

No PLL used, just 8MHz clock.

k, I give. how you plan on doing that?
0%, 100%, spikey 1% and spikey 99%?

[rmteo]

Set PR2=0, CCPRxL=0. (Leave prescaler at default 1:1).
Set CCP1CON<5:4> to 01,10 or 11 for 25%,50% or 75% duty cycle.

[skimask]

Set PR2=0, CCPRxL=0. (Leave prescaler at default 1:1).
Set CCP1CON<5:4> to 01,10 or 11 for 25%,50% or 75% duty cycle.

I dunno!!!

I could very well be wrong (in this particular, singular, one time case I don't think I am), but it looks to me (at least in the 18F4620 and 18F4685 datasheet) that Timer2 (which is the base timer for the CCP and ECCP) is driven off of the Fosc/4 (i.e. instruction cycle), therefore, 500khz is max.

See figure 15-3, Note 1, on page 144, of the PIC18F4620 datasheet (DS39626D)

-Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.

Also, see Equation 15-1 on the right side of that same page:

-When TMR2 is equal to PR2, the following three events occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into CCPRxH

Changing the CCP1 registers will only change frequency, not duty cycle, which won't change anyways because PR2 is 0.

I wish I was near my hardware so I could beat this up...try it out and break something!

But I was just thinking...if it actually did run 2Mhz, this might be a neat way to 'stack PWMs' (if that's even a word or a method of doing anything at all, maybe battery charging?).
You could have a hardware PWM buzzing along at 2Mhz at a few duty cycles, run that output into an AND gate, with the other input to the AND being run by a 'not so fast' software PWM, or even another PWM channel. Something like a boost-converter might benefit from a stacked PWM like that. Gotta have high freq to get good conversion efficiency...

[rmteo]

I thought so too. Anyway, I tried it and indeed you can get a 2MHz PWM with 3 different (4 if you include 0%) duty cycles with an 8MHz clock. Checked it out in hardware and on an oscope. I can post a picture of the scope but you said you can't see it.

With a 4x PLL, you can get a 8MHz PWM. Of course you can just use CLKO and get these frequencies, albeit without any duty cycle resolution.