18F2550 timing

[sstt1976]

I'm using an 18F2550 with a 20MHz oscillator and a DEFINE OSC 20 statement in my PBP program. I burn the chip with an HS setting and a /3(/2) scaler. Turns out this makes my circuit work exactly the way I'd like.

Now I want to burn the chip with an HSPLL setting and maintain the exact same internal timing for all my PBP instructions. I know that HSPLL automatically makes the 18F2550 run internally at 96MHz so I tried a /4(/3) scaler and a DEFINE OSC 48 statement but I can tell it's running slightly different than before.

How do I maintain the original internal timing? I need AD readings, pauseus, pause and all instructions to take the exact same time when I burn using HSPLL.

Thanks!

[skimask]

Now I want to burn the chip with an HSPLL setting and maintain the exact same internal timing for all my PBP instructions. I know that HSPLL automatically makes the 18F2550 run internally at 96MHz so I tried a /4(/3) scaler and a DEFINE OSC 48 statement but I can tell it's running slightly different than before.

HSPLL doesn't make it run at 96Mhz internally.
All HSPLL does is take the external (or internal) clock input and multiply it by 4. If you try to run the PIC at 96Mhz internally (i.e. using an external 24Mhz clock with HSPLL turned on), it won't run. The PIC is only spec'd to run at 48Mhz maximum. The HSPLL (assuming you're running an external clock) allows you to use a 12Mhz external clock to run the PIC at 48Mhz (assuming all of your dividers are set correctly). Using a 12Mhz (or lower) external clock is a lot easier to design and a lot less 'fussy' than trying to design around a 48Mhz external oscillator (which would most likely require a lot of shielding, grounding, and so on)...

[sstt1976]

The reason I thought the HSPLL for an 18F2550 ramped the crystal's signal up to 96MHz is from the datasheet which says...

"The PLL is enabled in HSPLL, XTPLL, ECPLL and ECPIO Oscillator modes. It is designed to produce a fixed 96MHz reference clock from a fixed 4MHz input."

...and then the Oscillator Configuration Options table shows 96MHz for Microcontroller Clock Frequency no matter what the Input Oscillator Frequency is when HSPLL is used. It shows different frequency options by way of scalers. The table also shows all the way up to 24MHz as viable Input Oscillator Frequency for HSPLL and an 18F2550.

I could just use trial and error with my DEFINE OSC statement until I get the exact same feel to my circuit but I wanted to understand this theoretically. I tried a DEFINE OSC 40 to account for your explanation but there is still something off from the original HS way it runs.

[skimask]

How far off is it?
If you did this...

main:
high LED
pause 500
low LED
pause 500
goto main

What do you end up with as far as timing goes? Should be a 1 second pulse, 1/2 on, 1/2 off, obviously...

[sstt1976]

I ran the test you suggested and here's what I found out:

18F2550 with a 20MHz xtal, HS, postscaler (/2), DEFINE OSC 20
makes 1ms into 4ms, which is what works perfectly for my situation.

18F2550 with 20MHz xtal, HSPLL, any possible postscaler, any possible DEFINE OSC
can't make 1ms into 4ms.

I would need to use either a higher than possible DEFINE OSC statement or a larger postscaler option. For example, DEFINE OSC 64 with postscaler (/6) would work but 64 isn't compiling.
A postscaler which is (/8) could help too but it's not an option.

Seems I should just use a different xtal. I could get that same 1ms becomes 4ms situation if I use a 12MHz or 24Mhz xtal for this circuit. Are 12 and 24 equally usable? Maybe 12 would be better because less noise?

[skimask]

18F2550 with 20MHz xtal, HSPLL, any possible postscaler, any possible DEFINE OSC can't make 1ms into 4ms.

Like I said before, you can't run a 20Mhz xtal into the HSPLL! The PIC is probably running on the backup internal oscillator (add some code to check for the oscillator fail bit and see what it reads back).