The reason I thought the HSPLL for an 18F2550 ramped the crystal's signal up to 96MHz is from the datasheet which says...

"The PLL is enabled in HSPLL, XTPLL, ECPLL and ECPIO Oscillator modes. It is designed to produce a fixed 96MHz reference clock from a fixed 4MHz input."

...and then the Oscillator Configuration Options table shows 96MHz for Microcontroller Clock Frequency no matter what the Input Oscillator Frequency is when HSPLL is used. It shows different frequency options by way of scalers. The table also shows all the way up to 24MHz as viable Input Oscillator Frequency for HSPLL and an 18F2550.

I could just use trial and error with my DEFINE OSC statement until I get the exact same feel to my circuit but I wanted to understand this theoretically. I tried a DEFINE OSC 40 to account for your explanation but there is still something off from the original HS way it runs.