Quote Originally Posted by xnihilo View Post
Well, it does not work as expected.

First I have a problem with the other interrupts (I poster a message today about this) but with my settings I was expecting a TMR0 overflow evey 10ms but it happens every 1ms...

TMR0 starts at 98, and I'm using a 8MHz intosc.
0.5Us per instruction cycle (FOSC/4).

Strange...
8,000,000 Hz oscillator / 4 = 2,000,000 instructions/second = 2,000,000 increments of TMR0 using a prescale of 1:1 (prescaler assigned to WDT).
TMR0 is an 8 bit timer, max count = 256. You're reloading it with 98, leaves you with 158 counts.
2,000,000 / 158 = 12,658.228 Hz = 79us per interrupt.
2,000,000 / 256 = 7812.5 Hz = 128us per interrupt.
So, you're 10ms theory (since we don't have any better information) isn't going to work.
But this might:
http://www.mister-e.org/pages/picmulticalcpag.html