Quote Originally Posted by xnihilo View Post
Define Osc 8

I assume it means clock speed is 8000000 clock cycles per 1000000 microseconds, thus 125ns clock cycles.
Right?
If tmr0 is updated at every clock cycle it takes 256*125ns to set the tmr0 overflow flag in intcon register. If I use a 1:256 prescaler, it will take 256*256*125ns (=8.192 ms) before tmr0 overflows.
Is that correct?
Datasheet reference one more time...
The PICs run at F(osc) / 4 , 4 clock cycles per instruction cycle. Therefore, at 4Mhz, the PIC executes 1 million single cycle instructions per second. At 8Mhz, 2 million single cycle instructions per second, 500ns per instruction cycle, which is what the timers are incremented from.

Tmr0 overflows every 256 instruction cycles, 7812.5 timers per second.
5 minutes = 300 seconds = 2,343,750 total overflows to get 5 minutes.
If Tmr0 is capable of 16 bit (as it is in some PICs), then 9155.2734375 overflows to get 5 minutes.