4 bit address decoding I2C chip

[skimask]

Thanks! I considered the dual-clock pin idea. Have you done this? I just can not affort to have anything get wiggled on the non-clocked port expanders.
How would you use a CE for the 23016s?
I have looked again on the web but have not found any 4 channel addressing port expanders! You would think one would be made by someone?

4 channel port expander...Try looking up 4 channel demultiplexer.

One idea I can think of off the top of my head is using 74LS154 - 4->16 demux chip...
Tie 4 'upper address lines' into A-B-C-D inputs of the '154, tie 3 more 'lower address lines' into all of the MCP23016's directly.
Put SCL onto G1 of the '154, tie G2 of the '154 low.
The outputs pins of the '154 (0-15) will go to the individual MCP23016's SCL pin. SDA is tied together across all devices.
(could also use a 74138 3-8 decoder, same logic applies)

Gives you 7 bits for addressing 16 individual lines (2^7 * 16 = 2048 possible lines).
Put the upper 4 bits into the '154....which will 'steer' the SCL to the appropriate bank of 8 MCP23016's.
Put the lower 3 bits into the 23016's....which will enable/select 1 of the 8 23016's in each bank...which also share the same SCL output pin from the '154.
Do whatever I2C commanding you need to do. The '154 effectively lets you toggle the SCL line on it's own output as selected by it's address pins.

One problem I see with this method is the fact that the SCL pulses will be delayed by a fraction of time due to the fact that they have to travel thru the '154. So, the I2C speed might have to be slowed down just a bit. Actually, it really shouldn't matter since the clock pulse will get there after the data bit...but you never know...

Then there's the matter of the pullups that'll be needed...and the device won't be able to hold the clock to slow it down...