Thanks for your wonderful help, Skimask.

I did find the datasheets, and it seems that the address valid to valid data time constraint was the most severe requirement. Using 70ns flash devices, I calculated that I could use a bus speed of 31.5MHz. However, the datasheet states that a bus speed of 25MHz should be used with external program memory.

Has anyone done similar calcs?

Thanks in advance
Mariusv