They are OR gates.
AND gates would be idle low so they wont work.
NAND gates would be idle high, but the 1s and 0s of the serial transmission would be inverted, so that wont help.
That is why I went with OR gates - idle high, non-inverted signal, logic 0 to enable, logic 1 to disable.
It seemed like a perfect plan, so i don't know whats going wrong.
Last edited by Kamikaze47; - 6th April 2008 at 14:31.
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