strange problem ! pic18f4550 & pic16f84a serial communication .

[leelion]

Hi
my code is simple as follow:

define osc 48
TRISB = $00 ' Set digit pins to output
mainloop:
toggle portB.5
pause 200
Goto mainloop ' Forever

End

my complier is PBPX 3.0.9.4
16Mhz crystal work with Pic18f4550
I measure portB.5 output led by scope, it toggle only every 20ms , only 1/10 of my seeting , how can i set exactly config for 16MHz crystal application to get precise output ?
I check PBP3\Device\PIC18F4550.PBPINC file internal seting just for 20Mhz
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; The #CONFIG block is passed directly to the asm file, but PBP will replace it
; automagically with the contents of a user-defined #CONFIG block if one is
; found in the PBP source program. There is no need to edit or comment this
; block in this file. Simply copy it to your source program and edit it there.
#CONFIG
CONFIG PLLDIV = 5 ; Divide by 5 (20 MHz oscillator input)
CONFIG CPUDIV = OSC1_PLL2 ; [Primary Oscillator Src: /1][96 MHz PLL Src: /2]
CONFIG USBDIV = 2 ; USB clock source comes from the 96 MHz PLL divided by 2
CONFIG FOSC = HSPLL_HS ; HS oscillator, PLL enabled (HSPLL)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ; Oscillator Switchover mode disabled
CONFIG PWRT = OFF ; PWRT disabled
CONFIG BOR = ON ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
CONFIG BORV = 3 ; Minimum setting
CONFIG VREGEN = ON ; USB voltage regulator enabled
CONFIG WDT = ON ; WDT enabled
CONFIG WDTPS = 512 ; 1:512
CONFIG CCP2MX = ON ; CCP2 input/output is multiplexed with RC1
CONFIG PBADEN = OFF ; PORTB<4:0> pins are configured as digital I/O on Reset
CONFIG LPT1OSC = OFF ; Timer1 configured for higher power operation
CONFIG MCLRE = ON ; MCLR pin enabled; RE3 input pin disabled
CONFIG STVREN = ON ; Stack full/underflow will cause Reset
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG ICPRT = OFF ; ICPORT disabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
CONFIG DEBUG = OFF ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) is not code-protected
CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) is not code-protected
CONFIG CP2 = OFF ; Block 2 (004000-005FFFh) is not code-protected
CONFIG CP3 = OFF ; Block 3 (006000-007FFFh) is not code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) is not code-protected
CONFIG CPD = OFF ; Data EEPROM is not code-protected
CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) is not write-protected
CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) is not write-protected
CONFIG WRT2 = OFF ; Block 2 (004000-005FFFh) is not write-protected
CONFIG WRT3 = OFF ; Block 3 (006000-007FFFh) is not write-protected
CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) are not write-protected
CONFIG WRTB = OFF ; Boot block (000000-0007FFh) is not write-protected
CONFIG WRTD = OFF ; Data EEPROM is not write-protected
CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
CONFIG EBTR2 = OFF ; Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks
CONFIG EBTR3 = OFF ; Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot block (000000-0007FFh) is not protected from table reads executed in other blocks
#ENDCONFIG
++++++++++++++++++++++++++++++++++++++++++++++++++ ++++
thanks

Lee

[richard]

when posting code please use code tags
http://www.picbasic.co.uk/forum/showthread.php?t=19594

#CONFIG
;wrong     CONFIG  PLLDIV = 5            ; Divide by 5 (20 MHz oscillator input)

    CONFIG  PLLDIV = 4            ; Divide by4 (16 MHz oscillator input)
    CONFIG  CPUDIV = OSC1_PLL2    ; [Primary Oscillator Src: /1][96 MHz PLL Src: /2]
    CONFIG  USBDIV = 2            ; USB clock source comes from the 96 MHz PLL divided by 2
    CONFIG  FOSC = HSPLL_HS       ; HS oscillator, PLL enabled (HSPLL)
    CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor disabled
    CONFIG  IESO = OFF            ; Oscillator Switchover mode disabled
    CONFIG  PWRT = OFF            ; PWRT disabled
    CONFIG  BOR = ON              ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
    CONFIG  BORV = 3              ; Minimum setting
    CONFIG  VREGEN = ON           ; USB voltage regulator enabled
    CONFIG  WDT = ON              ; WDT enabled
    CONFIG  WDTPS = 512           ; 1:512
    CONFIG  CCP2MX = ON           ; CCP2 input/output is multiplexed with RC1
    CONFIG  PBADEN = OFF          ; PORTB<4:0> pins are configured as digital I/O on Reset
    CONFIG  LPT1OSC = OFF         ; Timer1 configured for higher power operation
    CONFIG  MCLRE = ON            ; MCLR pin enabled; RE3 input pin disabled
    CONFIG  STVREN = ON           ; Stack full/underflow will cause Reset
    CONFIG  LVP = OFF             ; Single-Supply ICSP disabled
    CONFIG  ICPRT = OFF           ; ICPORT disabled
    CONFIG  XINST = OFF           ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
    CONFIG  DEBUG = OFF           ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
    CONFIG  CP0 = OFF             ; Block 0 (000800-001FFFh) is not code-protected
    CONFIG  CP1 = OFF             ; Block 1 (002000-003FFFh) is not code-protected
    CONFIG  CP2 = OFF             ; Block 2 (004000-005FFFh) is not code-protected
    CONFIG  CP3 = OFF             ; Block 3 (006000-007FFFh) is not code-protected
    CONFIG  CPB = OFF             ; Boot block (000000-0007FFh) is not code-protected
    CONFIG  CPD = OFF             ; Data EEPROM is not code-protected
    CONFIG  WRT0 = OFF            ; Block 0 (000800-001FFFh) is not write-protected
    CONFIG  WRT1 = OFF            ; Block 1 (002000-003FFFh) is not write-protected
    CONFIG  WRT2 = OFF            ; Block 2 (004000-005FFFh) is not write-protected
    CONFIG  WRT3 = OFF            ; Block 3 (006000-007FFFh) is not write-protected
    CONFIG  WRTC = OFF            ; Configuration registers (300000-3000FFh) are not write-protected
    CONFIG  WRTB = OFF            ; Boot block (000000-0007FFh) is not write-protected
    CONFIG  WRTD = OFF            ; Data EEPROM is not write-protected
    CONFIG  EBTR0 = OFF           ; Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
    CONFIG  EBTR1 = OFF           ; Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
    CONFIG  EBTR2 = OFF           ; Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks
    CONFIG  EBTR3 = OFF           ; Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks
    CONFIG  EBTRB = OFF           ; Boot block (000000-0007FFh) is not protected from table reads executed in other blocks
 #ENDCONFIG
 ++++++++++++++++++++++++++++++++++++++++++++++++++  ++++



 ;wrong  define osc 48   DEFINES ARE CASE SENSITIVE

define OSC 48 
 TRISB = $00        ' Set digit pins to output 
 mainloop:
  toggle portB.5 
  pause 200 
   Goto mainloop        ' Forever

   End