Apparantly even with A/D disabled it's still causing problems when you have AN2 & AN3
setup as Vref- & Vref+. Clearing ADCON1 bits 4 & 5 sets Vref to Vss & Vdd, and not these
pins.
The problem you describe sounds like read-modify-write, which is more of a problem when
an output has external capacitance on it. By having ADCON1.4 = 1, AN3 is connected to
an internal circuit for Vref+. This most likely is adding enough capacitance to cause the
read-modify-write issue.
What happens is when you set RA3, it does not change fast enough before you are setting
RA5, so RA3 is read back in, then writen again on the write to RA5 causing a 0 to be writen
back to RA3.
This would also explain why it works when you reverse the order. I.E. RA5=1 then RA3=1.
It works because the extra capacitance is not present on RA5.
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