Change;
TXLCD VAR PortA.3 'Puerto de TX del LCD
MCLRLCD VAR PortA.5 'Puerto de reset del LCD
to;
TXLCD VAR LATA.3 'Puerto de TX del LCD
MCLRLCD VAR LATA.5 'Puerto de reset del LCD
Does it work now?
Change;
TXLCD VAR PortA.3 'Puerto de TX del LCD
MCLRLCD VAR PortA.5 'Puerto de reset del LCD
to;
TXLCD VAR LATA.3 'Puerto de TX del LCD
MCLRLCD VAR LATA.5 'Puerto de reset del LCD
Does it work now?
Thank you for your help. We solved the problem.
I don't have an explanation, but it works now.
All I did was change ADCON1=B'00111111' to ADCON1=B'00001111'
And now it works just as expected on older and newer PICs.
I still am interested in an explanation, so if anyone would like to elaborate....
Thanks, Gabriel
Apparantly even with A/D disabled it's still causing problems when you have AN2 & AN3
setup as Vref- & Vref+. Clearing ADCON1 bits 4 & 5 sets Vref to Vss & Vdd, and not these
pins.
The problem you describe sounds like read-modify-write, which is more of a problem when
an output has external capacitance on it. By having ADCON1.4 = 1, AN3 is connected to
an internal circuit for Vref+. This most likely is adding enough capacitance to cause the
read-modify-write issue.
What happens is when you set RA3, it does not change fast enough before you are setting
RA5, so RA3 is read back in, then writen again on the write to RA5 causing a 0 to be writen
back to RA3.
This would also explain why it works when you reverse the order. I.E. RA5=1 then RA3=1.
It works because the extra capacitance is not present on RA5.
Last edited by Bruce; - 6th March 2008 at 00:27. Reason: P.S.
Thank you for your explanation.
I could not find this in the Errata for this PIC. Maybe it is not documented.
Gabriel
I doubt you will find anything on this in an errata doc. You should disconnect pins from the internal Vref circuit if they are not being used for Vref, and adjust your code as required to avoid read-modify-write problems.
Writing to the LAT registers VS port registers on the 18F series takes care of r-m-w.
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