Can't get 18F2221 PLL to run with INTOSC

[Charles Linquis]

ASM
ifndef __18F2221
error "Wrong Processor Type"
endif
ENDASM

DEFINE OSC 32
DEFINE NO_CLRWDT 1
DEFINE HSER_RCSTA 90H
DEFINE HSER_TXSTA 24H
DEFINE HSER_CLROERR 1
DEFINE LOADER_USED 1 ' Tell compiler to relocate code for bootloader
Define USE_LFSR 1



TRISA = %11111111
TRISB = %11111110
TRISC = %10111111

ADCON1 = $FF ' Start as all digital
CMCON = %00000111 ' No Comparator used, turn it off
ADCON2 = %10000110 ' Right Justify, /64
OSCTUNE =%01000000 ' bit 6 to turn on the PLL
OSCCON = %01110000 ' %11110000
TopLoop:
Toggle PORTB.0
PAUSE 10
GOTO TopLoop

[skimask]

So you're only getting about 12.5Hz on PortB.0?

[Charles Linquis]

Yes, and as I mentioned, I'm getting 2MHz out of OSC2. Since that is a /4 , the oscillator is in fact running 8. Only the PLL isn't working properly.

[skimask]

Yes, and as I mentioned, I'm getting 2MHz out of OSC2. Since that is a /4 , the oscillator is in fact running 8. Only the PLL isn't working properly.

I'm guessing here...the datasheet is a bit convoluted and jumps back and forth a bit...
2Mhz from OSC2 is right isn't it? OSC2 is FOsc/4, FOsc/4 is 8Mhz/4... System clock isn't FOsc in this case, it's the actual clock speed before the PLL...
Try that test program with
main:
High portb.0
pause 500
low portb.0
pause 500
goto main
.......just to see what happens. Should be one flash per second of course at 32Mhz. One flash every 4 seconds would certainly mean 8Mhz.


Also, I'm wondering if the bootloader is messing with your bits for you and shutting off your PLL!!!

[Bruce]

Have you tried OSCCON = %01110010?

[skimask]

Have you tried OSCCON = %01110010?

Don't I feel like a dipstick! Internal OSC block was never selected in the first place!!!

[Darrel Taylor]

Also, try putting the OSCCON statement before the OSCTUNE.

Additionally,
the PLL will only function when the selected output frequency
is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled and the PLLEN bit remains clear (writes are
ignored).

<br>

[Bruce]

Yep I think DT just nailed it. Might be holding it off until it's in the right mode for the switch.

[Charles Linquis]

Confirmed -

Darrel, you were right again. Now that I switch to 8MHz BEFORE I enable the PLL, it
works as expected.

Thanks!