
Originally Posted by
BrianT
I have a need for the lowest possible power draw. I think I can get away with a 100 KHz crystal and still get around the main loop in time. The defines for PBP stop at 3.58 or 4 MHz. There are no LCDs or serial datacomms to worry about.
I realise the bootloader can't work and I want to use ICSP via a modified EPIC for code load and dump.
Questions.
Can I use PBP with DEFINE OSC 4 and then fudge any timing loops by calling up a delay of 1/40th of what is needed? (4 MHz/40 = 100 KHz). For example calling up PAUSEUS 25 would in fact become a pause of 1 mSec.
Are there any other hidden little gotchas I should be aware of?
BrianT
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