Unwanted output signal jitter


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  1. #1
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    Quote Originally Posted by LinkMTech View Post
    Hello everyone,
    2. Scope screen shot of ouput signal with ON time delayed and with unwanted jitter at opposite end. If I turn the pot CCW from center, the output turn ON delay is increased from 0 to 500us.
    3. Scope screen shot of ouput signal with OFF time delayed and with unwanted jitter at opposite end. If I turn the pot CW from center, the output turn OFF delay is increased from 0 to 500us.
    The top trace (Yellow) is the input, bottom trace (Blue) is the output.
    Input signal is 5V with 2.5ms LOW pulse and 20K pull up, pot is a 5K from 5V to GND. Output driving a current limited LED at the moment.
    At first glance, your loops take different paths at different times, therefore, different numbers of instruction cycles. Look at your .lst file, count them up for the different if/then possibilities. You might need to throw a @nop in here or there to keep the timing correct.
    Your 'jitter' is 500ns, which happens to be one instruction cycle at 8Mhz (2Mhz instruction rate). Which also happens to be the difference between a NOP (one cycle) and a GOTO (2 cycles).

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    euhh 500 uSec Skimask, which is way over a NOP or GOTO
    Steve

    It's not a bug, it's a random feature.
    There's no problem, only learning opportunities.

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    Quote Originally Posted by mister_e View Post
    euhh 500 uSec Skimask, which is way over a NOP or GOTO
    Yep, sure is...but that u looked so much like an n.
    ...unless the PIC is running at 8Khz

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    Smile If only!

    Quote Originally Posted by skimask View Post
    Yep, sure is...but that u looked so much like an n.
    ...unless the PIC is running at 8Khz
    I'm glad I'm not the only one that sees things!

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    Lightbulb More info to consider

    Just remembered something about the jitter...
    If I commented the ADCIN command from the internal loop and just relied on the initial ADCIN read at the start of the program, the variable adjustment wouldn't work of course but be fixed at the pot setting instead and would get a clean output signal.
    I read through the ADC section of the data specs that specified Rs be less than 10K, my pot is 5K and left me thinking the sampling time has to be set correctly.
    Am I getting close or still wandering in the dark with a LED on a 2V battery?

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    [QUOTE=LinkMTech;48591]A couple of thoughts...

    Code:
    CLRW                    ' Clear all registers<<<-----CLRW works with PBP?
    
    ADCON1 = %00000000      '<<<---What's the default 'JUSTIFY' on a 16F737?
    
    DEFINE ADC_BITS     5                     <<<<---Why not use all 8 bits?
    -------and the manual says only 8,10,12...  I don't see 5 as a legal value
    
    Low_Adj var byte ' Input declared as byte size <<<-- You might want WORD here
    Low_set var word ' Input declared as byte size    <<<<- it is? :)
    
    Low_set = (abs(low_adj-128))*8      <<<<---these lines look a bit scary to me
    That last one...
    If you get a value above 32, when multiplied by 8 will overflow a byte variable. Low_set is a word, but low_adj isn't. I seem to have bad luck when mixing variable sizes like that. But that's just me...
    I think the ADC_BITS might be your killer. Keep it at 8 bits, AND out the low 3 bits, and shift it down by 3 bits.

    EDIT: Notice I changed OR to AND. My mistake..duhhhh...
    Last edited by skimask; - 4th January 2008 at 14:34.

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    Default My sleeves are rolled up again

    Thanks for the info Skimask.
    Yeah, some of my comments are left overs from the different attempts to feel my way through when thinking got too hard. Now I've got something else to study "Default Justify".
    I implemented all your suggestions except that one until I know what I'm doing.

    Thanks again,
    You guys rock!

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