Pin max current - short duration?

[kevj]

The data sheet specs 25 mA as the max current sourced by a pin. I'd like to source 75ma to 100ma, but for relatively short duration - say 20 uS max - in short groups of pulses (maybe 20 to 30 pulses together) followed by several seconds to several minutes of no pulses.

That's probably technically out of spec, but most LED's that spec 100 mA may spec up to 2A or more for short durations.

I wonder if the PIC is similar?

I know there is some variance between parts also - and I plan to make a bunch of these. Just because this current doesn't fry my prototype pics, doesn't mean it won't fry production units down the road - right?

Ideally I'd use a transistor but the prototype boards have already been run and it's wired direct and space is very limited for this application. Just wondering if it's at all safe or what I can expect as problems if we do run it and drop the resistance of the output low enough to generate the 75-100 Ma.

Thanks!

[skimask]

I think you're asking to basically shoot yourself in the foot...

The data sheet specs 25 mA as the max current sourced by a pin. I'd like to source 75ma to 100ma, but for relatively short duration - say 20 uS max - in short groups of pulses (maybe 20 to 30 pulses together) followed by several seconds to several minutes of no pulses.

What if the PIC locks up for some silly reason?

That's probably technically out of spec, but most LED's that spec 100 mA may spec up to 2A or more for short durations.

True...and I know I've shorted PIC output pins directly to ground before and pulled whatever current I could get out of them. The pins worked afterward...but for how long? I went to a 2 month class last year, had a load of slides that showed things like ESD damage, overvoltage/overcurrent damage, talked all about why things would work afterwards and fail some time after that.

Ideally I'd use a transistor but the prototype boards have already been run and it's wired direct and space is very limited for this application. Just wondering if it's at all safe or what I can expect as problems if we do run it and drop the resistance of the output low enough to generate the 75-100 Ma.

Got enough room to run a jumper wire and tie a few pins together and rewrite the firmware a bit? Not an optimal solution, but it might get you by...

[mister_e]

You could still cross your finger and use 3-4 I/O in parallel.. i'm not a fan of it.. but it could work. What you need to do is to set the according I/O to low and toggle their TRIS setting.

but.. come on.. sot-23 mosfet or digital transistor (yeah those with built-in base resistor) would never be that big to mess a PCB space

[skimask]

but.. come on.. sot-23 mosfet or digital transistor (yeah those with built-in base resistor) would never be that big to mess a PCB space

That's exactly the reason I started adding a load of extra thru-via's on my designs a few years ago, even if they're only connected to traces on one side of the PCB. I try to add at least one via near each and every pin on every component on a PCB, except the OSC lines of course. At least that way you can run a length of wire to a (insert part here) to fix up a problem like that, or in my case, you can cut 2 traces, and run 2 jumpers to cross a couple of RX/TX traces that got mislabeled during design. Might make the board a bit more electrically noisy (not sure, never had something like that tested), but it's saved my butt more than once.

[mister_e]

that's the real beauty to build some home-brew prototype before sending the Gerber file to the PCB shop

[duncan303]

Hi,

This relates to something I have been thinking about for while, and how i might be able to contribute back.

I too place through vias in tracks simply for the purpose of amending a design I will also place a Tee configuration of smd resistor pads especially on pins that I am not using, alowing me to tie down/up. However carefull I am to try and finalise a layout there will inevitably be a better way to execute a task, a constant cyclic routine of firmware vs components re-evaluation.

I recall a post recently, "why don't people use breadboards"....... well ,for me, breadboards are great for quiick evaluation of simple circiuts but inevitably they get crowded and the connections can be unreliable. The point for me is that the bench has far too may loose cables, clips, probes, blue tack. Actually my breadboard is handy because I can clamp it overhanging the bench and increase my working space...... and then I can hang even more cables over it when I'm not using it. The breadboard is a great tool, but can be given looks of derision when off the bench, it is also worth noting that some people can be a little scared of an electronics especially when you have invented something marvelous for the home environment.
"whats that thing doing, dear? are you sure its safe"!..........

anyway my point is that I have had in mind to create a panelised pcb layout for most of the pin count PICS and provide these as gerbers or jpgs for people to either have made up locally, or to be created with the most basic minimal equipment for example; exposure by the sun, increased footprint pad length (make smd easier with basic soldering iron),

from memory was it not sparkfun who started me on reflow with a domestic frying pan



OR are there just too many differrent permutations of the way people use PICS to make it worth while..

Or just put your breadboard in box!! simple solutions always best

Discuss

ps this should probably be in shematics

[Acetronics2]

from the Midrange Databook $30.5

Example Absolute Maximum Ratings†
Ambient temperature under bias........................................................................... . -55 to +125°C
Storage temperature .......................................................................................... -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ....................................................................... -0.3 to +7.5V
Voltage on MCLR with respect to VSS (2) ...................................................................... 0 to +14V
Voltage on RA4 with respect to Vss .............................................................................. 0 to +14V
Total power dissipation (1) .................................................................................................... 1.0W
Maximum current out of VSS pin ...................................................................................... 300 mA
Maximum current into VDD pin ......................................................................................... 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................. ± 20 mA
Maximum output current sunk by any I/O pin..................................................................... 25 mA
Maximum output current sourced by any I/O pin ............................................................... 25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined)............................. 200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) ....................... 200 mA
Maximum current sunk by PORTC and PORTD (combined) ........................................... 200 mA
Maximum current sourced by PORTC and PORTD (combined)...................................... 200 mA
Maximum current sourced by PORTC and PORTD (combined)...................................... 200 mA
Maximum current sourced by PORTF and PORTG (combined) ...................................... 100 mA
Maximum current sourced by PORTF and PORTG (combined) ...................................... 100 mA

just need to be read ...

ALSO WRITTEN: SEE PARTICULAR DATASHEETS ...

Means parallelling outputs ( or inputs ... why not ? ) is allowed ... You're right, Steve !!!
Alain