Need advice for creating nS time delay

[mister_e]

or... eh eh, a 18F and enable/disable the internal PLL on the fly...

[Darrel Taylor]

This won't help Sayzer, but it's another example of why NOT to say RTFD all the time.

I was looking at the timing of a 628A. Trying to see if there was something that might work.
Looked at the capacitor discharge idea using a on-board comparator. But the response time was up to 600ns.
Hmmm, didn't expect them to be that slow.

Then was looking farther and came across this ...
Apparently, you can run a 16F628A at 4Ghz.
A 1ns delay would just be a NOP.

[skimask]

??????????
http://www.picbasic.co.uk/forum/atta...5&d=1197319528

[Darrel Taylor]

I guess it should be RTFCD. (current datasheet)

P.S. Hello skimask.

[Ioannis]

Hi skimask! Where have you been? Its been a long time...

Well about the pin capacitance, I don't think it is a good idea in respect of the difference between chips. The delay won't be standard. If precision is needed don't think about it.

Can you provide more info about your project Sayzer?

Ioannis

[sayzer]

Ioannis,

I am interfacing with PYD1998 (digital output pyrodetector) and the communication requires a pause min.200nS.

I am using 12F675 (intosc) and the min. delay is 1uS.

1uS does not give precise results.
Since, a delay faster then 1uS at 4Mhz is not possible, now I have no choice but use a chip with 8Mhz intosc ( based on Alain's calculation I can get 500nS).

This time, the unit cost will be on table.

...
Then was looking farther and came across this ...
Apparently, you can run a 16F628A at 4Ghz.
A 1ns delay would just be a NOP.

Anyone can show me a practical application of this?


P.S. - Welcome back Skimask! Howzit?

[Ioannis]

Although I have not made anything on FPGA's I see them now as an approrpiate solution.

They can be really fast!

Now about the device, I could not find a detailed pdf. Only a 2-page short datasheet. Do you have a complete copy? From the short one I think it is not as fast as you have stated.

Ioannis