Catching a short spike / event?

[BrianT]

I scanned the PIC 18F4620 data sheet to see what they say about Interrupt-On-Change timing issues. Nothing except this in section 10.2.

.....The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>)......

This is vague but I interpret it as saying that the interrupt event must remain present on the pin until the processor gets around to reading the port a second time as directed by some of your instructions.

The comparator is 'analog' with a response time between 150 and 600 nSecs according to table 26.2. The comparator signal would be volatile unless you wired the comparator to have significant hysteresis.

HTH
Brian