Hmmm....
Suppose I have 8 ADC running at 10 bit and then do some math with the values, then output it to 8 HPWM on a chip like 18f4431, total code around 8k byte, will 8mhz internal osc be sufficient, or will there be a lag somewhere ?
Hmmm....
Suppose I have 8 ADC running at 10 bit and then do some math with the values, then output it to 8 HPWM on a chip like 18f4431, total code around 8k byte, will 8mhz internal osc be sufficient, or will there be a lag somewhere ?
ALL digital systems have delays and they are almost always variable depending where in the code loop the event you are looking for takes place.
Assume each ADC takes 50 uSec, 100 instructions of maths at 1 uS per instruction per channel, then 8 writes to the HPWM outputs each at 50 uSecs. Yes your mileage will vary but these values are in the ball park.
That makes a complete cycle of 8 inputs to 8 outputs about 400 uSecs for the ADC, 800 uSecs for the maths, plus a further 400 uSecs for the HPWM writes. 1600 uSecs - say 2 mSecs to be safe. If your code does nothing other than scan 8 inputs and write 8 HPWM outputs there will be up to about 2 mSecs delay from input to output.
You will have to decide if your application can live with that.
Cheers
Brian
Thanks Brian,
Yes , this is what I meant.
You said it will be about 2 ms delay from input to output, is it based on 8 Mhz oscillator ?
If I want to change the delay to 1 ms, is it as simple as to change the oscillator to 16 Mhz ?
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