Cannot compile for 40MHz 4 x pll

[BigWumpus]

Trying to track the reason for the continuous reset I display the values for
Power-on-reset (POR), Brown-out reset (BOR) , stack full reset (STKFUL) and stack underflow reset (STKUNF) bits, but all are showing to be zero after each reset, so that does not seem to be the problem?

WDT ?

Missing Loop ?


You have to write down all the CONFIG-Lines for all Config-registers !
You have to read the other lines inside the files too !

[passion1]

BigWumpus

Thank you for the advice!
Everything is working now!!