System Wide Clock?

[SOMRU]

Good morning,
Yes all pics are set to HS, double checked I/O's.
Oscillators defined at 20 MHz.
I will check board for ground leakage on that net.
Thanks for the quick response.
This forum is BRILLIANT!!

[SOMRU]

Good Afternoon,
Rerouted clock signal in several different configurations, serial/parallel and can still only get 3 of the five to roll. Am able to swap the last three around on end of run, same-same diag program and I/O, same results.
Went as far to hard wire the clock signals off board to eliminate stray capacitances.
Well.....
Back to the bench.
Should the the clock signal have the same voltage all the way down the line?? I would think so.
Going to replace crystal, caps, and main pic next.

Close but not quite ready for the BFH.

[SOMRU]

Well the BFH "Bottle of Fermented Hops" didn't hurt or help. But was enjoyable.

I gave in guys...

Tacked on some crystals and caps, trimmed some traces, and I'm up and running.

Started out with 20Mhz @ 4v PK2PK. Was getting about 1v drop for each pic in series or parallel. The pics start failing at 2.8v pk2pk.

I will not let this drop. I am just on a really tight schedule.

Thanks for the help so far.

[Art]

You can use a 74HC04 to distribute clock signal.
Like in this schematic:
http://www.picbasic.co.uk/forum/atta...4&d=1060366548
there is two pics, only one clock. More pics could be added.

[SOMRU]

thanks...

Possibly in the "NEXT GENERATION" upcoming.

How much SNYCH is really needed?
Not much for this application. But need for a solid timing freq is.


THANKS AGAIN