An EE friend of mine (Thanks Doug) told me a new possibility about the cause of the problem:

What if reading the ADC so often does not give it enough time to handle the low voltage values?

(more discussions via chat with my friend)

He points out something interesting, the test program initializes the ADC using:

DEFINE ADC_BITS 10 ' ADCIN resolution (Bits)
DEFINE ADC_CLOCK 1 ' ADC clock source (Fosc/8)
DEFINE ADC_SAMPLEUS 11 ' ADC sampling time (uSec)

But reading the pic basic manual we have:

ADC_SAMPLEUS is the number of microseconds the program waits
between setting the Channel and starting the analog to digital
conversion. This is the sampling time. The minimum number of
microseconds usable is determined by the minimum time for PAUSEUS.
See it’s section for this information.
and the PAUSEUS section says:
For 4mhz Minimum Delay is 24us
So, the initial theory appears to be right, I don't have the protoboard here now, but I will check this tomorrow.


Pablo