Handeling multiple Interrupts

[skimask]

Now that I think about it, skimask
The timer0 interrupt is the one not being delt with and not the other way around. If the tmr0 int happens more often then I would expect to see it happen and maybe miss the others.

Would you not agree?

Isn't that what I said?

"TMR0 interrupts happen a lot more often than TMR1."

The only reason I said TMR0 would happen more often is because it's 8 bit (usually). At any rate, you probably need to re-enter the interrupt routine to check on other interrupt sources in case they happen in the middle of your initial interrupt routine.