Adcin or Pot

[peterdeco1]

Check your statement TRISA=1. I believe you are making all PORTA as outputs except PORTA.0.

[mister_e]

Yup but POT 'Should' do the job... As output first to charge/discharge the capacitor, then set as input to evaluate the RC plah plah.

If the POT/Capacitors value match is not good AND the 'way to use them' is not good... of course results will be bad.

[sayzer]

In the schematic above, why the POT is connected to +5V ?

Any particular reason?

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[Archangel]

Are you using a linear taper Pot? Audio taper pots have a logarithmic scale to their resistance and would likely present a similar responce.
JS

[malc-c]

Well, I ordered them as Lin pots.. but knowing the numbskulls in the local shop they could well indeed be log

[lerameur]

I am using a 47K linear POT.
I tries usin a 0.1 UF capacitor, I was barely moving the pot and it reaches 255, bu adding 2 0.1 uF in series I was getting a little bit further. Then any changes in pot values did not change a thing. Decreasing the scale also help going a bi further. I scaled it down to decimal 2 (out of 255) and 2 x 0.1 uF caps. i am only getting halfway with the pot. i would like to go all the way.... what should I try..

[skimask]

I am using a 47K linear POT.
I tries usin a 0.1 UF capacitor, I was barely moving the pot and it reaches 255, bu adding 2 0.1 uF in series I was getting a little bit further. Then any changes in pot values did not change a thing. Decreasing the scale also help going a bi further. I scaled it down to decimal 2 (out of 255) and 2 x 0.1 uF caps. i am only getting halfway with the pot. i would like to go all the way.... what should I try..

What are your Vref+ and Vref- settings on?