Adcin or Pot


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  1. #1
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    Depending of your PIC, your ADCON, ANSEL setting have to be set to make AN0, AN1 as analog first. Your sampling time and clock source look fine... even if they are way too slow. Too slow is still better than to fast, so it's not your problem source here.

    Your pot have to be connected between Vdd and Vss. The wiper goes to the PIC input. It's value must be equal OR less than the maximum recommended by your datasheet. It's a good idea to filter the POT output with a capacitor (10-100 nF)
    Steve

    It's not a bug, it's a random feature.
    There's no problem, only learning opportunities.

  2. #2
    malc-c's Avatar
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    I tend to use a 10k Lin pot with one leg connected to +ve (5v) and a 0.1uf cap between the other leg and GND - the wiper then goes to the PIN.

    Using the scale value in the POT statement you should be able to get the range right so the value is 0 at one end of the travel, to 255 at the other.

    Edit - just noticed that you have an LCD attached - then using
    Code:
    Pot PORTA.0,scale,D
    LCDOUT $FE,$C0, "Cal value " ,#D    ; where D is the varible used in the POT statement
    would show the value for the variable D in deceimal on the second line, so you can calibrate the range exactly
    Last edited by malc-c; - 7th January 2007 at 22:13.

  3. #3
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    I barely turn the Pot and it reaches goes from 0 to 255 in no time, I mean barely, I tried all the values for the sale ranging from 0 to 255 passing through 127, it react the same way.
    My left leg of the pot is on GRD the middle is on the pin, and right leg on the Vcc. with 0.1uF cap gnd to pin.
    is that it ?

    i kept is very simple:

    INCLUDE "modedefs.bas"
    DEFINE OSC 20 'use external 20mhz crystal
    CMCON = 7 : ANSEL = 0 : ADCON1 = 7
    DEFINE LCD_DREG PORTB ' Set LCD Data port
    DEFINE LCD_DBIT 4 ' Set starting Data bit (0 or 4) if 4-bit bus
    DEFINE LCD_RSREG PORTB ' Set LCD Register Select port
    DEFINE LCD_RSBIT 1 ' Set LCD Register Select bit
    DEFINE LCD_EREG PORTB ' Set LCD Enable port
    DEFINE LCD_EBIT 0 ' Set LCD Enable bit
    DEFINE LCD_BITS 4 ' Set LCD bus size (4 or 8 bits)
    DEFINE LCD_LINES 2 ' Set number of lines on LCD
    DEFINE LCD_COMMANDUS 2500
    DEFINE LCD_DATAUS 250
    DEFINE CHAR_PACING 2000


    TRISB = 0
    TRISA = 1
    '27
    temp var word : right var byte : left var Byte : oldright var byte : oldleft var byte

    loop:


    oldright = right 'Pot reading 1
    oldleft = left 'Pot reading 2

    Pot PORTA.0,127,right
    Pot PORTA.1,127,left
    right = (right +oldright)/2 'Reducing the fluctuating output by taking an average
    left = (left +oldleft)/2

    Lcdout $fe, 1 'Clear screen
    Lcdout "Right: ", Dec right 'Display the decimal value
    Lcdout $fe, $C0, "Left: ", DEC left 'Display the decimal value
    pause 100

    goto loop
    end

  4. #4
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    if you're using POT you have it wrong. look in the PBP manual. Depending your POT impedance, the capacitor might be too low... i hate POT. your PIC have ADCs.... just use it with ADCIN and set the according i/o properly.
    Steve

    It's not a bug, it's a random feature.
    There's no problem, only learning opportunities.

  5. #5
    malc-c's Avatar
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    Quote Originally Posted by lerameur View Post
    My left leg of the pot is on GRD the middle is on the pin, and right leg on the Vcc. with 0.1uF cap gnd to pin.
    is that it ?
    If I read this correctly you have placed the capacitor in parallel with the left leg of the pot. If so this is wrong, you need to place it in series with the pot.

    Using a 10K lin pot and a 0.1uf capacitor and a scale of 254 I get a range of 0 - 255 in the last 30% of travel, regardless of the value of scale. However, if a lower value of scale is used, the travel range is reduced, but with a higher value I get the full range (0 - 255) within this 30% of travel. I think that the choice of potentiometer and or the value of the capacitor used is critical if you want to get a full range across 100% of the travel of the pot.
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    Last edited by malc-c; - 8th January 2007 at 10:29.

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    Check your statement TRISA=1. I believe you are making all PORTA as outputs except PORTA.0.

  7. #7
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    Yup but POT 'Should' do the job... As output first to charge/discharge the capacitor, then set as input to evaluate the RC plah plah.

    If the POT/Capacitors value match is not good AND the 'way to use them' is not good... of course results will be bad.
    Steve

    It's not a bug, it's a random feature.
    There's no problem, only learning opportunities.

  8. #8
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    In the schematic above, why the POT is connected to +5V ?

    Any particular reason?

    ------------------

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