Here are a few examples of how to use the new #CONFIG block syntax for PBP3. (This will NOT work on previous versions of PBP ... Get your upgrade now 
)
PBP3 makes it a little easier to figure out, and set up your configs. It has eliminated the need to comment out the default configurations set up by PBP. It still has default settings - these can be found in the /PBP3/DEVICES file under yourchip.PBPINC . Here is an example of default settings for the PIC18F45K22:
Code:
; CUT rest of file out for display purposes
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; The #CONFIG block is passed directly to the asm file, but PBP will replace it
; automagically with the contents of a user-defined #CONFIG block if one is
; found in the PBP source program.
#CONFIG
__CONFIG _CONFIG1H, _FOSC_INTIO67_1H
__CONFIG _CONFIG3H, _PBADEN_OFF_3H
__CONFIG _CONFIG4L, _LVP_OFF_4L & _XINST_OFF_4L
#ENDCONFIG
; CUT rest of file out for display purposes
If you want to change the default configs in PBP3, DON'T edit the above file. You can just declare them in your code using the #CONFIG #ENDCONFIG block. For all the possibilities of config settings for your chip, check out the /PBP3/DEVICE_REFERENCE folder, and select the yourchip.INFO file. It will look something like this:
Code:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; File: PIC18F45K22.INFO
; Date: 07/24/11
; Generated by melabs File Manager
;
; PICBASIC PRO(tm) Compiler version: 3.0.0.x
;
; Copyright 2011 microEngineering Labs, Inc. All Rights Reserved
; The content herein is intended to facilitate embedded development using
; PICBASIC PRO Compiler. Reproduction or utilization for other purposes
; is prohibited without written permission from microEngineering Labs, Inc..
;
; microEngineering Labs, Inc.
; 2845 Ore Mill Road STE 4
; Colorado Springs, CO 80904
; 719-520-5323
; fax: 719-520-1867
; http://melabs.com
; [email protected]
;
; Modifications to this file in the \DEVICE_REFERENCE folder will be overwritten when
; you install future upgrades.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;MPASM CONFIG Directive Options
;
; This section is included for reference only. The following options may
; be used with the MPASM CONFIG directive to specify configuration settings
; in the source program using the #CONFIG/#ENDCONFIG block.
; Example:
;
; #CONFIG
; CONFIG OSC = HS
; CONFIG WDTE = ON
; #ENDCONFIG
;
;
; Oscillator Selection bits
; CONFIG FOSC = RC ;111X External RC oscillator, CLKOUT function on RA6
; CONFIG FOSC = ECLPIO6 ;EC oscillator (low power, <500 kHz)
; CONFIG FOSC = ECLP ;EC oscillator, CLKOUT function on OSC2 (low power, <500 kHz)
; CONFIG FOSC = ECMPIO6 ;EC oscillator (medium power, 500 kHz-16 MHz)
; CONFIG FOSC = ECMP ;EC oscillator, CLKOUT function on OSC2 (medium power, 500 kHz-16 MHz)
; CONFIG FOSC = INTIO7 ;Internal oscillator block, CLKOUT function on OSC2
; CONFIG FOSC = INTIO67 ;Internal oscillator block
; CONFIG FOSC = RCIO6 ;External RC oscillator
; CONFIG FOSC = RC ;External RC oscillator, CLKOUT function on OSC2
; CONFIG FOSC = ECHPIO6 ;EC oscillator (high power, >16 MHz)
; CONFIG FOSC = ECHP ;EC oscillator, CLKOUT function on OSC2 (high power, >16 MHz)
; CONFIG FOSC = HSMP ;HS oscillator (medium power 4-16 MHz)
; CONFIG FOSC = HSHP ;HS oscillator (high power > 16 MHz)
; CONFIG FOSC = XT ;XT oscillator
; CONFIG FOSC = LP ;LP oscillator
;
; 4X PLL Enable
; CONFIG PLLCFG = OFF ;Oscillator used directly
; CONFIG PLLCFG = ON ;Oscillator multiplied by 4
;
; Primary clock enable bit
; CONFIG PRICLKEN = OFF ;Primary clock can be disabled by software
; CONFIG PRICLKEN = ON ;Primary clock is always enabled
;
; Fail-Safe Clock Monitor Enable bit
; CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled
; CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled
;
; Internal/External Oscillator Switchover bit
; CONFIG IESO = OFF ;Oscillator Switchover mode disabled
; CONFIG IESO = ON ;Oscillator Switchover mode enabled
;
; Power-up Timer Enable bit
; CONFIG PWRTEN = OFF ;Power up timer disabled
; CONFIG PWRTEN = ON ;Power up timer enabled
;
; Brown-out Reset Enable bits
; CONFIG BOREN = SBORDIS ;Brown-out Reset enabled in hardware only (SBOREN is disabled)
; CONFIG BOREN = NOSLP ;Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
; CONFIG BOREN = ON ;Brown-out Reset enabled and controlled by software (SBOREN is enabled)
; CONFIG BOREN = OFF ;Brown-out Reset disabled in hardware and software
;
; Brown Out Reset Voltage bits
; CONFIG BORV = 190 ;VBOR set to 1.90 V nominal
; CONFIG BORV = 220 ;VBOR set to 2.20 V nominal
; CONFIG BORV = 250 ;VBOR set to 2.50 V nominal
; CONFIG BORV = 285 ;VBOR set to 2.85 V nominal
;
; Watchdog Timer Enable bits
; CONFIG WDTEN = ON ;WDT is always enabled. SWDTEN bit has no effect
; CONFIG WDTEN = SWON ;WDT is controlled by SWDTEN bit of the WDTCON register
; CONFIG WDTEN = NOSLP ;WDT is disabled in sleep, otherwise enabled. SWDTEN bit has no effect
; CONFIG WDTEN = OFF ;Watch dog timer is always disabled. SWDTEN has no effect.
;
; Watchdog Timer Postscale Select bits
; CONFIG WDTPS = 32768 ;1:32768
; CONFIG WDTPS = 16384 ;1:16384
; CONFIG WDTPS = 8192 ;1:8192
; CONFIG WDTPS = 4096 ;1:4096
; CONFIG WDTPS = 2048 ;1:2048
; CONFIG WDTPS = 1024 ;1:1024
; CONFIG WDTPS = 512 ;1:512
; CONFIG WDTPS = 256 ;1:256
; CONFIG WDTPS = 128 ;1:128
; CONFIG WDTPS = 64 ;1:64
; CONFIG WDTPS = 32 ;1:32
; CONFIG WDTPS = 16 ;1:16
; CONFIG WDTPS = 8 ;1:8
; CONFIG WDTPS = 4 ;1:4
; CONFIG WDTPS = 2 ;1:2
; CONFIG WDTPS = 1 ;1:1
;
; CCP2 MUX bit
; CONFIG CCP2MX = PORTC1 ;CCP2 input/output is multiplexed with RC1
; CONFIG CCP2MX = PORTB3 ;CCP2 input/output is multiplexed with RB3
;
; PORTB A/D Enable bit
; CONFIG PBADEN = ON ;PORTB<5:0> pins are configured as analog input channels on Reset
; CONFIG PBADEN = OFF ;PORTB<5:0> pins are configured as digital I/O on Reset
;
; P3A/CCP3 Mux bit
; CONFIG CCP3MX = PORTB5 ;P3A/CCP3 input/output is multiplexed with RB5
; CONFIG CCP3MX = PORTE0 ;P3A/CCP3 input/output is mulitplexed with RE0
;
; HFINTOSC Fast Start-up
; CONFIG HFOFST = ON ;HFINTOSC output and ready status are not delayed by the oscillator stable status
; CONFIG HFOFST = OFF ;HFINTOSC output and ready status are delayed by the oscillator stable status
;
; Timer3 Clock input mux bit
; CONFIG T3CMX = PORTC0 ;T3CKI is on RC0
; CONFIG T3CMX = PORTB5 ;T3CKI is on RB5
;
; ECCP2 B output mux bit
; CONFIG P2BMX = PORTD2 ;P2B is on RD2
; CONFIG P2BMX = PORTC0 ;P2B is on RC0
;
; MCLR Pin Enable bit
; CONFIG MCLRE = EXTMCLR ;MCLR pin enabled, RE3 input pin disabled
; CONFIG MCLRE = INTMCLR ;RE3 input pin enabled; MCLR disabled
;
; Stack Full/Underflow Reset Enable bit
; CONFIG STVREN = ON ;Stack full/underflow will cause Reset
; CONFIG STVREN = OFF ;Stack full/underflow will not cause Reset
;
; Single-Supply ICSP Enable bit
; CONFIG LVP = ON ;Single-Supply ICSP enabled if MCLRE is also 1
; CONFIG LVP = OFF ;Single-Supply ICSP disabled
;
; Extended Instruction Set Enable bit
; CONFIG XINST = ON ;Instruction set extension and Indexed Addressing mode enabled
; CONFIG XINST = OFF ;Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
;
; Background Debug
; CONFIG DEBUG = OFF ;Disabled
; CONFIG DEBUG = ON ;Enabled
;
; Code Protection Block 0
; CONFIG CP0 = OFF ;Block 0 (000800-001FFFh) not code-protected
; CONFIG CP0 = ON ;Block 0 (000800-001FFFh) code-protected
;
; Code Protection Block 1
; CONFIG CP1 = OFF ;Block 1 (002000-003FFFh) not code-protected
; CONFIG CP1 = ON ;Block 1 (002000-003FFFh) code-protected
;
; Code Protection Block 2
; CONFIG CP2 = OFF ;Block 2 (004000-005FFFh) not code-protected
; CONFIG CP2 = ON ;Block 2 (004000-005FFFh) code-protected
;
; Code Protection Block 3
; CONFIG CP3 = OFF ;Block 3 (006000-007FFFh) not code-protected
; CONFIG CP3 = ON ;Block 3 (006000-007FFFh) code-protected
;
; Boot Block Code Protection bit
; CONFIG CPB = OFF ;Boot block (000000-0007FFh) not code-protected
; CONFIG CPB = ON ;Boot block (000000-0007FFh) code-protected
;
; Data EEPROM Code Protection bit
; CONFIG CPD = OFF ;Data EEPROM not code-protected
; CONFIG CPD = ON ;Data EEPROM code-protected
;
; Write Protection Block 0
; CONFIG WRT0 = OFF ;Block 0 (000800-001FFFh) not write-protected
; CONFIG WRT0 = ON ;Block 0 (000800-001FFFh) write-protected
;
; Write Protection Block 1
; CONFIG WRT1 = OFF ;Block 1 (002000-003FFFh) not write-protected
; CONFIG WRT1 = ON ;Block 1 (002000-003FFFh) write-protected
;
; Write Protection Block 2
; CONFIG WRT2 = OFF ;Block 2 (004000-005FFFh) not write-protected
; CONFIG WRT2 = ON ;Block 2 (004000-005FFFh) write-protected
;
; Write Protection Block 3
; CONFIG WRT3 = OFF ;Block 3 (006000-007FFFh) not write-protected
; CONFIG WRT3 = ON ;Block 3 (006000-007FFFh) write-protected
;
; Configuration Register Write Protection bit
; CONFIG WRTC = OFF ;Configuration registers (300000-3000FFh) not write-protected
; CONFIG WRTC = ON ;Configuration registers (300000-3000FFh) write-protected
;
; Boot Block Write Protection bit
; CONFIG WRTB = OFF ;Boot Block (000000-0007FFh) not write-protected
; CONFIG WRTB = ON ;Boot Block (000000-0007FFh) write-protected
;
; Data EEPROM Write Protection bit
; CONFIG WRTD = OFF ;Data EEPROM not write-protected
; CONFIG WRTD = ON ;Data EEPROM write-protected
;
; Table Read Protection Block 0
; CONFIG EBTR0 = OFF ;Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
; CONFIG EBTR0 = ON ;Block 0 (000800-001FFFh) protected from table reads executed in other blocks
;
; Table Read Protection Block 1
; CONFIG EBTR1 = OFF ;Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
; CONFIG EBTR1 = ON ;Block 1 (002000-003FFFh) protected from table reads executed in other blocks
;
; Table Read Protection Block 2
; CONFIG EBTR2 = OFF ;Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
; CONFIG EBTR2 = ON ;Block 2 (004000-005FFFh) protected from table reads executed in other blocks
;
; Table Read Protection Block 3
; CONFIG EBTR3 = OFF ;Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
; CONFIG EBTR3 = ON ;Block 3 (006000-007FFFh) protected from table reads executed in other blocks
;
; Boot Block Table Read Protection bit
; CONFIG EBTRB = OFF ;Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
; CONFIG EBTRB = ON ;Boot Block (000000-0007FFh) protected from table reads executed in other blocks
;
;
;/MPASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Here is an example of how to use the #CONFIG block:
Code:
' PIC18F45K22 With Internal OSC set to 64 Mhz
' FLASH AN LED CONNECTED TO PORTB.0
#CONFIG
CONFIG DEBUG = OFF
CONFIG XINST = OFF
CONFIG STVREN = OFF
CONFIG WDTEN = OFF
CONFIG FCMEN = OFF
CONFIG FOSC = INTIO67
CONFIG PLLCFG = ON
CONFIG PRICLKEN = ON
CONFIG IESO = OFF ; Two-Speed Start-up disabled
CONFIG WDTPS = 128 ; 1:128 prescaller for watchdog
CONFIG BOREN = OFF ; Brown-out Reset disabled in hardware and software
CONFIG BORV = 250 ; VBOR set to 2.5 V nominal
CONFIG MCLRE = EXTMCLR ; MCLR pin enabled, RE3 input pin disabled
CONFIG HFOFST = OFF ; The system clock is held off until the HF-INTOSC is stable.
CONFIG PBADEN = OFF ; PORTB<4:0> pins are configured as digital I/O on Reset
CONFIG CCP2MX = PORTC1 ; CCP2 input/output is multiplexed with RC1
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected
CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) not code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected
CONFIG CPD = OFF ; Data eeprom not code-protected
CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) not write-protected
CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) not write-protected
CONFIG WRT2 = OFF ; Block 2 (4000h-5FFFh) not write-protected
CONFIG WRT3 = OFF ; Block 3 (6000h-7FFFh) not write-protected
CONFIG WRTB = OFF ; Boot block (000000-0007FFh) not write-protected
CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected
CONFIG WRTD = OFF ; Data eeprom not write-protected
CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
#ENDCONFIG
DEFINE OSC 64 'THE 16MHz IS PLL'ed TO 64 MHz
OSCCON = %01110000 'Set internal osc to 16 Mhz
OSCTUNE = %01000000 'Turn PLL ON to multiply osc by 4
ANSELA = 0 'ALL ANALOG TO DIGITAL
ANSELB = 0
ANSELC = 0
If you get an error like:
[ERROR] program.pbp fatal (34) : Block overflow for #ENCONFIG
that means that there are too many comments in your configs to "fit". Erase some comments and try compiling again.
Some new features in PBP3 make it possible to do conditional defines, and conditional PIC setup.
(Some content plagiarized from here: http://support.melabs.com/threads/26...wfull=1#post38 ... Thanks Darrel!)
Here's an example of how you can set the configuration bits according to the chip being compiled for.
It uses the Conditional Compile directives (#IF/#ELSE/#ENDIF) along with the #CONFIG blocks.
Only the configs for the selected chip will be used.
And if any other chip besides the 25K20 or 25K22 are selected, it will give an error.
Code:
#IF __PROCESSOR__ = "18F25K22"
#config
CONFIG FOSC = HSHP
CONFIG WDTEN = OFF
CONFIG PWRTEN = ON
CONFIG BOREN = OFF
CONFIG PBADEN = OFF
CONFIG MCLRE = INTMCLR
CONFIG LVP = OFF
CONFIG DEBUG = OFF
CONFIG XINST = OFF
#endconfig
ANSELA = 0 ; All Digital
ANSELB = 0
ANSELC = 0
#ELSE
#IF __PROCESSOR__ = "18F25K20"
#config
CONFIG FOSC = HS
CONFIG WDTEN = OFF
CONFIG PWRT = ON
CONFIG BOREN = OFF
CONFIG PBADEN = OFF
CONFIG MCLRE = OFF
CONFIG LVP = OFF
CONFIG DEBUG = OFF
CONFIG XINST = OFF
#endconfig
ANSEL = 0 ; All Digital
ANSELH = 0
#ELSE
#ERROR "This program does not support the " + __PROCESSOR__
#ENDIF
#ENDIF
Note that it also sets the ANSEL? registers differently for each chip. Anything else specific to a particular chip can be set this way too.
Some things to remember:
PBP can not use the XINST ,"Instuction set extension and indexed addressing mode", so make sure it is never turned on.
LVP is another issue. Just leave this off as well.
Some older chips like a slightly different context. Let's take a PIC16F628A for example:
Here are the default configs:
Code:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; The #CONFIG block is passed directly to the asm file, but PBP will replace it
; automagically with the contents of a user-defined #CONFIG block if one is
; found in the PBP source program.
#CONFIG
ifdef PM_USED
device pic16F628A, xt_osc, wdt_on, mclr_on, lvp_off, protect_off
else
__config _XT_OSC & _WDT_ON & _MCLRE_ON & _LVP_OFF & _CP_OFF
endif
#ENDCONFIG
(The first part of this conditional config statment checks to see if the PM assembler is used. Since code for the newer chips can't be assembled with PM, I always chose MPASM.)
You have to use a format like this for these older chips: __config _x & _y & _z
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