Tissy... are you saying that modifying and saving your C:\PBP\18F2550.INC as follow
Code:
;****************************************************************
;*  18F2550.INC                                                 *
;*                                                              *
;*  By        : Leonard Zerman, Jeff Schmoyer                   *
;*  Notice    : Copyright (c) 2004 microEngineering Labs, Inc.  *
;*              All Rights Reserved                             *
;*  Date      : 12/31/04                                        *
;*  Version   : 2.46                                            *
;*  Notes     :                                                 *
;****************************************************************
        NOLIST
    ifdef PM_USED
        LIST
        "Error: PM does not support this device.  Use MPASM."
        NOLIST
    else
        LIST
        LIST p = 18F2550, r = dec, w = -311, f = inhx32
        INCLUDE "P18F2550.INC"	; MPASM  Header
        ;__CONFIG    _CONFIG1L, _PLLDIV_5_1L & _CPUDIV_OSC1_PLL2_1L & _USBDIV_2_1L
        ;__CONFIG    _CONFIG1H, _FOSC_HSPLL_HS_1H
        ;__CONFIG    _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H
        ;__CONFIG    _CONFIG3H, _PBADEN_OFF_3H
        ;__CONFIG    _CONFIG4L, _LVP_OFF_4L & _ICPRT_OFF_4L & _XINST_OFF_4L
        NOLIST
    endif
        LIST
EEPROM_START	EQU	0F00000h
BLOCK_SIZE	EQU	32
And use the following fuse setting...
Code:
    asm
         CONFIG PLLDIV = 12         ; 96 MHz PLL Prescaler: Divide by 12 (48 MHz input)
         CONFIG CPUDIV = OSC1_PLL2  ; System Clock Postscaler: [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
         CONFIG USBDIV = 2          ; Full-Speed USB Clock Source: 96 MHz PLL/2                ;
         CONFIG FOSC = HS           ; HS oscillator, HS used by USB         
         CONFIG FCMEM = ON          ; Fail-Safe Clock Monitor enabled
         CONFIG IESO = OFF          ; Internal/External Switch Over Disabled
         CONFIG PWRT = ON           ; Power-up Timer enabled
         CONFIG BOR = ON_ACTIVE     ; Brown-out Reset Enabled when the device is not 
         CONFIG BORV = 43           ; Brown-out Voltage: 4.3V
         CONFIG VREGEN = ON         ; USB Voltage Regulator Enabled
         CONFIG WDT = ON            ; Watchdog timer =  HW Enabled - SW Disabled
         CONFIG WDTPS = 128         ; Watchdog Postscaler = 1:128
         CONFIG MCLRE = ON          ; MCLR Enabled
         CONFIG LPT1OSC = OFF       ; Timer1 oscillator configured for high power       
         CONFIG PBADEN = OFF        ; PORTB<4:0> pins are configured as digital I/O on Reset   
         CONFIG CCP2MX = OFF        ; CCP2 input/output is multiplexed with RB3
         CONFIG STVREN = OFF        ; Stack Overflow Reset Disabled
         CONFIG LVP = OFF           ; Low Voltage Programming Disabled
         CONFIG ICPRT = OFF         ; In-Circuit Debug/Programming Disabled      
         CONFIG XINST = ON          ; Extended Instruction Set Enabled
         CONFIG DEBUG = OFF         ; Background Debugger Disabled      
         CONFIG CP0 = OFF           ; Code Protection Block 0 Disabled
         CONFIG CP1 = OFF           ; Code Protection Block 1 Disabled
         CONFIG CP2 = OFF           ; Code Protection Block 2 Disabled
         CONFIG CP3 = OFF           ; Code Protection Block 3 Disabled
         CONFIG CPB = OFF           ; Boot Block Code Protection Disabled
         CONFIG CPD = OFF           ; Data EEPROM Code Protection Disabled
         CONFIG WRT0 = OFF          ; Write Protection Block 0 Disabled
         CONFIG WRT1 = OFF          ; Write Protection Block 1 Disabled
         CONFIG WRT2 = OFF          ; Write Protection Block 2 Disabled
         CONFIG WRT3 = OFF          ; Write Protection Block 3 Disabled
         CONFIG WRTB = OFF          ; Boot Block Write Protection Disabled
         CONFIG WRTC = OFF          ; Configuration Register Write Protection Disabled
         CONFIG WRTD = OFF          ; Data EEPROM Write Protection Disabled
         CONFIG EBTR0 = OFF         ; Table Read Protection Block 0 Disabled
         CONFIG EBTR1 = OFF         ; Table Read Protection Block 1 Disabled
         CONFIG EBTR2 = OFF         ; Table Read Protection Block 2 Disabled
         CONFIG EBTR3 = OFF         ; Table Read Protection Block 3 Disabled
         CONFIG EBTRB = OFF         ; Boot Block Table Read Protection Disabled
    ENDASM
it works here...